Abstract: A chip detection method includes: providing a chip to be tested, the chip having multiple one-time programmable memories (OTPMs); transmitting a test signal to the chip to maintain the OTPMs in the chip in a latched state; and detecting whether the chip emits a low-light signal, and if yes, determining that an OTPM is leaky. The chip detection method and device can detect an OTPM that is burnt through by mistake, and can also detect an OTPM that has slight leakage, thereby preventing a defective product with a potential burn-through risk from entering a subsequent production process.

Abstract: Disclosed are an active region, an active region array and a formation method thereof. The active region is formed in a substrate. The active region is provided with a wordline structure. The wordline structure penetrates the active region in a first direction and divides the active region into a source region and a drain region. The source region and the drain region are arranged in a second direction, and a size of the drain region in a third direction is greater than that of the source region in the third direction. An angle between the first direction and the second direction is an acute angle, and the third direction is perpendicular to the second direction.

Abstract: A method for pushing a key includes the following steps: setting a plurality of keys, each of which corresponds to a different encrypted environment; configuring a user terminal with an environment switching interface for selection of an encrypted environment; and pushing a corresponding key to the user terminal according to a received key acquisition request.

Abstract: A method and device for enhancing alignment performance of a lithographic device can provide an optimal alignment light source type to perform alignment according to product features. Overlay performance of the product can be improved, wafer reject can be reduced, and production efficiency can be enhanced.

Abstract: A wafer edge exposure apparatus includes a wafer carrying module, a reticle, a reticle driving module, an alignment module, an exposure module, and a control module; the wafer carrying module is configured to carry the wafer and drive the wafer to rotate; the wafer includes a valid region and an edge region surrounding the valid region; the reticle driving module is configured to drive the reticle to rotate; the alignment unit is configured to detect the alignment state of the reticle with the wafer; and the control module is configured to control the movement state of the wafer carrying module and the reticle driving module and configured to control the exposure module to perform wafer edge exposure on the wafer.

Abstract: The present application relates to a movable buffer, an automated material handling system and a corresponding overhead hoist transfer. The movable buffer includes: an inclined track including a first end and a second end opposite to each other, wherein the second end of the inclined track is higher than the first end of the inclined track; a storage tray connected to the inclined track, wherein the storage tray is provided with a space for accommodating a front opening unified pod, the storage tray is provided with at least one opening; and a transmission mechanism, wherein the upper surface of the transmission mechanism is connected to the lower surface of the overhead buffer, the lower surface of the transmission mechanism is connected to the inclined track, and the transmission mechanism is used for driving the storage tray to slide from the first end of the inclined track to the second end.

Abstract: A semiconductor structure includes a base and conductive channel structure which includes first and second conductive channel layers and conductive buffer layer. The first conductive channel layer includes a first conductive channel, first and second doped regions on both sides of the first conductive channel; the second conductive channel layer includes a second conductive channel and third and fourth doped regions on both sides of the second conductive channel; the conductive buffer layer reduces electrical interference between the first and third doped regions. The semiconductor structure further includes a first wire layer disposed on the base extending in a direction and in contact with the second doped region; a second wire layer extending in another direction and in contact with the first and third doped regions; and a gate structure disposed around the first and second conductive channels.

Abstract: In the present application, the automatic cleaner comprises a housing, a first pipeline for extracting liquid from a bucket to be cleaned, and a second pipeline for injecting detergent into the bucket to be cleaned; the first pipeline and the second pipeline are both disposed on an inner wall of the housing, and the housing is configured to be enclosed to form a receiving space for receiving the bucket to be cleaned.

Abstract: Sense amplifier, memory and control method are provided. The sense amplifier includes: amplify module configured to amplify voltage difference between bit line and reference bit line when the sense amplifier is in amplifying stage; write module connected to the bit line and the reference bit line, and configured to pull the voltage difference between the bit line and the reference bit line according to data to be written when the sense amplifier is in write stage; controllable power module connected to the amplify module, configured to provide first voltage to the amplify module when the sense amplifier is in non-write stage, and to provide second voltage to the amplify module when the sense amplifier in write stage. Herein, the second voltage is less than the first voltage, and the second voltage is in positive correlation with the drive capability of the write module.

Abstract: A data transmission circuit includes: a comparison circuit, configured to compare received first data on a data bus with received second data on a global data line and output a comparison result of whether a number of different bits between the first data and the second data exceeds a preset threshold; a data conversion circuit, configured to: if the comparison result indicates that the number of different bits exceeds the preset threshold, invert the first data and transmit the inverted first data to the global data line, and otherwise, transmit the first data to the global data line; and a read-write conversion circuit, configured to: if the comparison result indicates that the number of different bits exceeds the preset threshold, transmit data on the global data line to a complementary local data line, and otherwise, transmit data on the global data line to a local data line.

Abstract: A sense amplifier includes: an amplification module, configured to amplify a voltage difference between a bit line and a reference bit line when the sense amplifier is in an amplification phase; a controllable power module, connected to the amplification module and configured to supply a first voltage to the amplification module when the sense amplifier is in a writing phase, and supply a second voltage to the amplification module when the sense amplifier is in a non-writing phase, and the second voltage is greater than the first voltage; and a writing module, connected to the bit line and the reference bit line and configured to pull the voltage difference between the bit line and the reference bit line according to to-be-written data when the sense amplifier is in the writing phase.

Abstract: A method may include orienting a set of solar power units in a first position in which rows of solar power units are shaded by adjacent rows of solar power units; and monitoring energy generated by the set of solar power units over a window of time, that includes from when the set of solar power units are oriented in the first position until a sun angle corresponds to none of the rows being shaded by the adjacent rows. The method may include identifying a knee in energy generation during the first window of time, where the knee indicates a transition from higher to lower rates of change of energy generation at a given solar angle. The method may include plotting a trajectory of future orientation positions over time of the set of solar power units that include an orientation and time corresponding to the given solar angle.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and relates to the field of semiconductor technologies. A manufacturing method includes: providing a substrate; forming a metal wiring layer on the substrate; etching the metal wiring layer to form a plurality of spaced metal interconnection structures; forming a first dielectric layer on a side wall of each metal interconnection structure and a surface of the metal interconnection structure away from the substrate; and depositing a second dielectric layer in a gap between the metal interconnection structures, the second dielectric layer covering the first dielectric layer, and the first dielectric layer and the second dielectric layer being both made of materials with low dielectric constants. The manufacturing method according to the present disclosure may reduce a parasitic capacitance and power consumption of the device, and improve a product stability.

Abstract: A semiconductor structure includes a substrate, bit line structures, and capacitor connection lines. A plurality of bit line structures are arranged on the substrate. Contact holes are formed between adjacent bit line structures. A capacitor connection line includes a first conductive block and a second conductive block. The first conductive block and the second conductive block are sequentially filled in a contact hole. A chamfered structure is formed on a top end of the first conductive block. The chamfered structure is adjacent to a bit line structure. A bottom end of the second conductive block matches the chambered structure.

Abstract: Embodiments in accordance with the present disclosure are directed to configuring an analyzer apparatus for processing a particular sample-processing cartridge. The analyzer apparatus includes a portable container and sample-specific configuration circuitry. The portable container supports and integrates a sample-processing cartridge and the sample-specific configuration circuitry. The sample-specific configuration circuitry identifies configuration information specific to the sample-processing cartridge and configures the analyzer apparatus for a series of state configurations.

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.

Abstract: Aspects of a storage device including a memory and a controller are provided which reduces or eliminates garbage collection in zoned namespace (ZNS) architectures by mapping zones to sub-blocks of blocks of the memory. Each zone includes a plurality of logical addresses. The controller determines a number of open zones, and maps the open zones to the sub-blocks in response to the number of open zones meeting a threshold. Thus, larger numbers of open blocks typically present in ZNS may be reduced, and increased block sizes due to scaling may be accommodated in ZNS. In some aspects, the controller receives a request from a host device to write data associated with the zones in sub-blocks, and maps each of the zones to at least one of the sub-blocks in response to the request. The request may indicate zones are partially unused. Thus, out of zone conditions may also be avoided.

Abstract: A comparator includes: a first stage circuit, configured to receive a voltage signal to be compared and a reference voltage signal Vref, and to generate and output a first amplifying signal and a second amplifying signal based on the voltage signal to be compared and the reference voltage signal Vref; a second stage circuit, connected with the first stage circuit, configured to generate and latch a first output signal and a second output signal based on the first amplifying signal and the second amplifying signal; wherein the first stage circuit and/or the second stage circuit include(s) a first pair of cross-coupled transistors.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow sub-blocks with different sub-block addresses to be linked across multiple planes to form metablocks. The memory includes multiple blocks in different planes, where each of the blocks includes multiple sub-blocks. The controller links a first sub-block in a first plane and a second sub-block in a second plane with different sub-block addresses to form the metablock. After forming the metablock, the controller programs different word lines in the first and second sub-blocks when writing data to the metablock. Thus, the controller may write data to linked or relinked metablocks with different sub-block addresses, thereby improving die yield and memory capacity of the storage device.

Abstract: A radiation therapy system comprises a magnetic resonance imaging (MRI) system combined with an irradiation system, which can include one or more linear accelerators (linacs) that can emit respective radiation beams suitable for radiation therapy. The MRI system includes a split magnet system, comprising first and second main magnets separated by gap. A gantry is positioned in the gap between the main MRI magnets and supports the linac(s) of the irradiation system. The gantry is rotatable independently of the MRI system and can angularly reposition the linac(s). Shielding can also be provided in the form of magnetic and/or RF shielding. Magnetic shielding can be provided for shielding the linac(s) from the magnetic field generated by the MRI magnets. RF shielding can be provided for shielding the MRI system from RF radiation from the linac.