Patents Assigned to TECHNOLOGIES INC.
  • Patent number: 9467469
    Abstract: According to certain non-limiting embodiments disclosed herein, the functionality of a server is extended with a mechanism for identifying connections with clients that have exhibited attack characteristics (for example, characteristics indicating a DoS attack), and for transitioning internal ownership of those connections such that server resources consumed by the connection are reduced, while keeping the connection open. The connection thus moves from a state of relatively high resource use to a state of relatively low server resource use. According to certain non-limiting embodiments disclosed herein, the functionality of a server is extended by enabling the server to determine that any of a client and a connection exhibits one or more attack characteristics (e.g., based on at least one of client attributes, connection attributes, and client behavior during the connection, or otherwise). As a result of the determination, the server changes its treatment of the connection.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: October 11, 2016
    Assignee: AKAMAI TECHNOLOGIES, INC.
    Inventors: Sudhin Mishra, Stephen L. Ludin, Philip A. Lisiecki, Erik Nygren, John A. Dilley, Karl-Eliv J. Hallin, Joshua Hunt
  • Patent number: 9465988
    Abstract: An electronic device including an illuminator and a camera configured for performing iris recognition while the user holds the device. The lens of the camera comprises four molded plastic elements with eight aspheric surfaces at a total thickness of only 3.4 mm that provides a mildly distorted image 1.2 mm across. The relative aperture is 3.5 with a fixed focal distance, providing a depth-of-field spanning a fixed focus region of at least 10 cm in depth that is 25 to 35 cm (centimeters) from the eye. The illuminator comprises a near-IR LED in a Cassegrain telescope configuration for efficient directing of flux toward the eye, thereby conserving device volume and electric energy use.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 11, 2016
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Eric Gifford Marason, Serkan Hatipoglu, Miguel Virgen
  • Patent number: 9467455
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for network risk assessment. One of the methods includes obtaining information describing network traffic between a plurality of network devices within a network. A network topology of the network is determined based on the information describing network traffic, with the network topology including nodes connected by an edge to one or more other nodes, and with each node being associated with one or more network devices. Indications of user access rights of users are associated to respective nodes included in the network topology. User interface data associated with the network topology is generated.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: October 11, 2016
    Assignee: PALANTIR TECHNOLOGIES INC.
    Inventors: Miles Seiver, Charles Rosenblum
  • Patent number: 9465538
    Abstract: A flash memory control method, storing a logical-to-physical address mapping relationship between a host and a flash memory and a root table in the flash memory and providing a non-volatile storage area storing a root table pointer. A mapping relationship pointer is set forth in the root table to show where the logical-to-physical address mapping relationship is stored in the flash memory. The root table pointer points to the root table stored in the flash memory. In response to a power restoration request issued from the host, the flash memory is accessed based on the root table pointer and thereby the root table is read and the logical-to-physical address mapping relationship is retrieved from the flash memory based on the mapping relationship pointer set forth in the root table.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: October 11, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Yi-Lin Lai
  • Patent number: 9466442
    Abstract: A locking switch assembly includes a locking switch having a locking plunger, and an actuator has a housing and a cover. The actuator has a through hole, and the through hole receives the locking plunger. The actuator having a non-access mode and an access mode, and at least one of the housing or the cover is configured to change from the non-access mode to the access mode. The housing or the cover has a cap, and at least a portion of the cap prevents access to the through hole in the non-access mode.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: October 11, 2016
    Assignee: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Roberto S. Santos, Elik I. Fooks
  • Patent number: 9467289
    Abstract: A network security system comprises a first component that generates an address for identifying a communicating device on a network. A second component receives the address generated by the first component and facilitates transitioning from an existent address to the generated address. Such transitioning is effectuated in order to protect the network against attack while providing seamless communications with respect to the communicating device.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: October 11, 2016
    Assignee: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Mark B. Anderson, David D. Brandt, Ramdas M. Pai, Taryl J. Jasper
  • Patent number: 9463916
    Abstract: A high temperature film substrate having a seal material printed thereon in a predefined pattern. The film comprises a pliable high melt temperature substrate and a heat-seal material selectively coated onto the substrate only in an area predetermined to be heat sealed together. Also disclosed is a heat-sealed pouch comprising a pliable high melt temperature substrate and a heat-seal material selectively coated onto the substrate only in a heat sealed area.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: October 11, 2016
    Assignee: B.S.C. TECHNOLOGIES, INC.
    Inventor: Robert J. Cohn
  • Patent number: 9467656
    Abstract: A method and apparatus for facilitating audio communication remotely with a person includes the use of several observation devices, each having an audio system that can play audio signals and receive acoustic signals and convert them to audio signals. The audio signals are wirelessly communicated in the region via a wireless local area network, and outside of the region by a wide area network via a gateway device. The audio signals from a command console located remotely from the region are playing in a synchronizations by several of the observation devices such that the resulting acoustic signals combine additively at the location of a person in the region with whom communication is conducted. The observation devices are designed to be deployed on an ad hoc basis to facilitate rapid deployment of the system.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 11, 2016
    Assignee: VSN TECHNOLOGIES, INC.
    Inventor: Gustavo Leizerovich
  • Patent number: 9465172
    Abstract: An optical fiber connector comprises: a positioning housing that has a recessed open end; a positioning cover that is formed with at least two first grooves and at least two second grooves; and at least two terminal plugs, each of which has a plug housing and an end sleeve. The positioning cover is detachably mountable on the positioning housing between first and second positions relative to the positioning housing to cover the recessed open end. The end sleeves are respectively fitted into the first grooves when the positioning cover is disposed at the first position, and are respectively fitted into the second grooves when the positioning cover is disposed at the second position.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: October 11, 2016
    Assignees: FIBERON TECHNOLOGIES INC., BAYCOM OPTO-ELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Hsi-Chung Shih
  • Patent number: 9465432
    Abstract: A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: October 11, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 9465557
    Abstract: A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 11, 2016
    Assignee: DIABLO TECHNOLOGIES INC.
    Inventors: Maher Amer, Michael Lewis Takefman
  • Patent number: 9466321
    Abstract: Systems, apparatuses, and methods use angular position tracking in mitigating data loss risks stemming from adjacent track interference (ATI), wide area track erasure (WATER), and/or other issues. A storage device includes a rotational magnetic storage medium divided into a group of tracks and a controller communicably coupled to the rotational magnetic storage medium. The controller is configured to: determine, based on an angular position of a write operation within a group of tracks, whether the angular position of the write operation overlaps a previously written area in the group of tracks; in the event the angular position of the write operation overlaps the previously written area in the group of tracks, increment a counter; and in the event the counter exceeds a counter threshold, perform a data loss risk mitigation procedure.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: October 11, 2016
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Wayne H. Vinson, Marika Meertens, Edwin S. Olds
  • Publication number: 20160293264
    Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.
    Type: Application
    Filed: October 30, 2015
    Publication date: October 6, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Ali Al-Shamma, Farookh Moogat, Chang Siau, Grishma Shah, Kenneth Louie, Khanh Nguyen, Kapil Verma
  • Publication number: 20160291883
    Abstract: A memory system may use adaptive trimming to control throughput and traffic from the host to/from the memory. The trimming parameters of memory may be adaptively changed based on the data rate from the host. The programming speed may be slowed in order to reduce wear and improve endurance. In particular, the data rate for the transfer of data from a data buffer to the memory (e.g. NAND flash) may be matched to the host data rate. This programming speed reduction may be triggered upon prediction of idle times in the host bus.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 6, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Abhijeet Manohar, Daniel Tuers, Sathyanarayanan Subramanian, Judah Gamliel Hahn
  • Patent number: 9460385
    Abstract: Apparatus and methods for activity based plasticity in a spiking neuron network adapted to process sensory input. In one approach, the plasticity mechanism of a connection may comprise a causal potentiation portion and an anti-causal portion. The anti-causal portion, corresponding to the input into a neuron occurring after the neuron response, may be configured based on the prior activity of the neuron. When the neuron is in low activity state, the connection, when active, may be potentiated by a base amount. When the neuron activity increases due to another input, the efficacy of the connection, if active, may be reduced proportionally to the neuron activity. Such functionality may enable the network to maintain strong, albeit inactive, connections available for use for extended intervals.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: October 4, 2016
    Assignee: QUALCOMM TECHNOLOGIES INC.
    Inventors: Filip Piekniewski, Micah Richert, Eugene Izhikevich, Victor Hokkiu Chan, Jeffrey Alexander Levin
  • Patent number: 9460387
    Abstract: Event-based updates in artificial neuron networks may be implemented. An internal event may be defined in order to update incoming connections of a neuron. The internal event may be triggered by an external signal and/or internally by the neuron. A reinforcement signal may be used to trigger an internal event of a neuron in order to perform synaptic updates without necessitating post-synaptic response. An external event may be defined in order to deliver response of the neuron to desired targets. The external and internal events may be combined into a composite event configured to effectuate connection update and spike delivery to post-synaptic target. The scope of the internal event may comprise the respective neuron and does not extend to other neurons of the network. Conversely, the scope of the external event may extend to other neurons of the network via, for example, post-synaptic spike delivery.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: October 4, 2016
    Assignee: QUALCOMM TECHNOLOGIES INC.
    Inventors: Oleg Sinyavskiy, Eugene Izhikevich
  • Patent number: 9459933
    Abstract: A distributed work processing system for processing computational tasks IS scalable and fault-tolerant without requiring centralized control. Worker processes running on worker hosts and worker coordinators running on worker coordinator hosts interact with a task store that holds a collection of tasks to be performed by a logical group of worker processes, a lock database used for locking the logical group for coordination by one worker coordinator process at a time, a membership store that contains mappings of worker processes to logical groups, and an assignment store indicating which tasks are assigned to which workers. The worker coordinator process has a scanner process to deal with unassigned tasks and deduplicating duplicate assignments. If a worker coordinator does not see enough worker processes, it can instantiate more. If a worker process does not see a worker coordinator, it can instantiate one.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: October 4, 2016
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: AndyGibb Halim, Swapneel Patil
  • Patent number: 9460038
    Abstract: Microprocessors with multi-core dies that include bypass buses are provided. Each microprocessor comprises a plurality of physical pins for coupling the microprocessor to a processor bus coupled to a chipset. The multi-core die has at least two complementary sets of one or more processing cores, each providing a bus interface coupling respective core inputs and outputs to corresponding processor bus lines. A bypass bus on the die enables cores of the complementary sets to bypass the processor bus and communicate directly with each other. The bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus. Moreover, the microprocessor is operable to detect whether the chipset or a complementary core is driving the processor bus, and if the latter, to select the higher quality bypass bus signals over the corresponding processor bus signals.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: October 4, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Darius D. Gaskins
  • Patent number: 9456836
    Abstract: One aspect of the present disclosure includes a neurostimulator delivery apparatus. The apparatus includes a handle portion, an elongate shaft extending from the handle portion, and a distal deployment portion. The distal deployment portion is configured to releasably mate with a neurostimulator. The neurostimulator is sized and configured for implantation into a craniofacial region of a subject.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: October 4, 2016
    Assignee: AUTONOMIC TECHNOLOGIES, INC.
    Inventors: Carl Lance Boling, Anthony V. Caparso, Ryan Powell, Jennifer Teng, Morgan Clyburn
  • Patent number: 9458155
    Abstract: This disclosure is directed to pyrido[4,3-b]indoles having rigid moieties. The compounds in one embodiment are pyrido[4,3-b]indoles having an unsaturated hydrocarbon moiety. The compounds in another embodiment are pyrido[4,3-b]indoles having a cycloalkyl, cycloalkenyl or heterocyclyl moiety. Pharmaceutical compositions comprising the compounds are also provided, as are methods of using the compounds in a variety of therapeutic applications, including the treatment of a cognitive disorder, psychotic disorder, neurotransmitter-mediated disorder and/or a neuronal disorder.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: October 4, 2016
    Assignee: MEDIVATION TECHNOLOGIES, INC
    Inventors: David T. Hung, Andrew A. Protter, Rajendra Parasmal Jain, Sarvajit Chakravarty