Abstract: A radio-frequency (RF) energy coupling apparatus for electromagnetic interference (EMI) susceptibility testing of a device. The apparatus includes a ground-plane, a micro-strip, a first dielectric layer, a coupling-strip, and a second dielectric layer. The micro-strip overlies the ground-plane. The first dielectric layer is interposed between the ground-plane and the micro-strip. The combination of the ground-plane, the micro-strip, and the first dielectric layer cooperate to form a micro-strip transmission line configured to propagate RF energy from a RF generator to a termination load. The coupling-strip overlies the micro-strip opposite the first dielectric layer. The coupling-strip is configured to couple RF energy from the micro-strip to a harness wire connected to the device. The second dielectric layer is interposed between the coupling-strip and the micro-strip.

Abstract: A system for performing optical spectroscopy measurements includes a light source for generating an input optical beam and an interferometer. The interferometer includes a beam splitter that splits the input optical beam into first and second light beams; a first light path that directs the first light beam through a sample containing an analyte to a first output port; and a second light path that directs the second light beam to the first output port. At least one of the first and second light paths adjusts a relative phase of a corresponding one of the first and second light beams, so that the first and second light beams are out of phase at the first output port, substantially canceling background light and outputting sample light corresponding to a portion of the first light signal absorbed by the sample in the sample cell. A detection system detects the output sample light.

Abstract: A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

Abstract: A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency.

Abstract: A method and apparatus for selectively actuating a downhole tool in a tubular conduit. An actuator tool has an actuator mandrel having an actuator bore through and a bypass and a profile key to selectively engage the downhole tool. The downhole tool has one or more profile receivers adapted to actuate the downhole tool. The actuator tool is conveyed into the tubular conduit and the actuator tool and the downhole tool are engaged if the profile key and the profile receiver match, and the actuator tool and the downhole tool are non-engaged if the profile key and the profile receiver do not match. Fluid may be circulated through the actuator bore to flush or wash ahead of the actuator tool.

Abstract: A system and method to prevent merchandise from being left at a checkout counter includes a first step of entering a checkout area with a group of items having identification tags. A next step includes reading the tags of the items in the group. A next step includes associating the tagged items as a group. A next step includes detecting whether any tagged item is separated from the group. A next step includes generating an alert if any tagged item is separated from the group.

Abstract: A method for playing an original playlist and for substituting alternate versions of the songs during playback is disclosed. The user can set the extent to which the number and type of alternate versions are substituted into the original playlist.

Abstract: A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.

Abstract: An improved apparatus, system, and method for removing debris from lightweight components are disclosed. The improved apparatus can include an air mover, a cyclonic chamber in fluid communication with the air mover, an enclosure component operably attached with the cyclonic chamber, and a debris collection component in fluid communication with the cyclonic chamber. The lightweight components positioned inside the cyclonic chamber can be moved, rotated, or carried by cyclonic airflow, causing the lightweight components to hit against one another or against the sidewall, so as to separate the debris clung thereto.

Abstract: A microprocessor includes a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores. At least one of the plurality of processing cores is configured to write a patch to the memory. The patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores.

Abstract: A linear light-emitting diode (LED)-based solid-state lamp using an AC current control scheme and shock protection switches operates normally with an electronic ballast. Due to the use of shock protection switches in the two lamp bases at two opposite ends, the ballast-compatible LED lamp fully protects a person from possible electric shock during initial installation, maintenance, and re-lamping no matter what the rated power and the brand of the LLT lamp are and no matter whether the electronic ballast is existing used ones that may be incompatible with the lamp or faulty, leading to an unacceptable leakage current.

Abstract: A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

Abstract: Data to be stored in a nonvolatile memory array may be compressed in a manner that provides variable sized portions of compressed data, which is then padded to a predetermined uniform size and then stripped of padding. The encoded compressed data is sent to the memory array where it is stored in a uniform sized area that is exclusive to the encoded compressed data.

Abstract: According to the disclosure hereof, the functionality of a server can be extended to collect data on content streams that the server is delivering to clients, and to beacon certain data back an analytics system to facilitate monitoring of, reporting on, and analysis of the delivery of content streams. At various stages of the streaming process, a server can read and update state information (for example cookie data) on the requesting client reflecting, for example, status in playing a particular stream. Based on the client's requests and the state information at each stage, the server can beacon appropriate information about the stream and its playback status back to the analytics system. The teachings hereof are particularly useful, without limitation, in streaming media analytics and for segment-based streaming approaches, including over HTTP.

Abstract: A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor.

Abstract: Methods for manufacturing non-volatile memory devices including peripheral transistors with reduced and less variable gate resistance are described. In some embodiments, a NAND-type flash memory may include floating-gate transistors and peripheral transistors (or non-floating-gate transistors). The peripheral transistors may include select gate transistors (e.g., drain-side select gates and/or source-side select gates) and/or logic transistors that reside outside of a memory array region. A floating-gate transistor may include a floating gate of a first conductivity type (e.g., n-type) and a control gate including a lower portion of a second conductivity type different from the first conductivity type (e.g., p-type). A peripheral transistor may include a gate including a first layer of the first conductivity type, a second layer of the second conductivity type, and a cutout region including one or more sidewall diffusion barriers that extends through the second layer and a portion of the first layer.

Abstract: A deflection or snap fit type latch system can resist separation in at least three axes. The snap fit type latch system can include a first member and a second member that when engaged are configured to form a snap fit connection, at least one of the members comprising a deflecting arm. A tee feature on the first member can include a stem and a head. A slot on the second member can slidingly receive the stem of the tee feature as the first and second members engage such that the second member is sandwiched between the first member and the head of the tee feature. The snap fit connection can resist separation in a first axis and the combined tee feature and slot resist separation in two additional axes. The snap fit type latch system can be part of an enclosure, such as a storage device.

Abstract: A system for improving a sensing ability of an interlock switch system may include an interlock switch and a target component. The interlock switch may include a first antenna coil that may receive one or more signals from one or more antenna coils within a sensing range of the first antenna coil. The target component may include an actuator that may interface with the interlock switch. The target component may also include at least two antenna coils. Each of the at least two antenna coils may then include an electronic identification (ID) associated with the target component.