Abstract: A sampling gate comprising a first frequency input coupled to a first frequency path from a broadband photodiode. The sampling gate also includes a positive bias input coupled to a positive offset portion of a second frequency path from the broadband photodiode. The sampling gate also includes a negative bias input coupled to a negative offset portion of the second frequency path from the broadband photodiode. The sampling gate combines a first frequency signal from the first frequency path and a second frequency signal from the second frequency path to create a combined broadband frequency signal from the broadband photodiode.

Abstract: A vector network analyzer (VNA) can include a control processor, a receiver coupled with the control processor, switching circuitry coupled with the receiver, a radio frequency (RF) bridge coupled with the switching circuitry, a transmission line coupled with the RF bridge, wherein the transmission line is configured to be coupled with a load; and a signal generator coupled with the RF bridge.

Abstract: A current sensor configured to measure current in a current-carrying conductor. The current sensor includes a Rogowski coil having plurality of conductor segments. The plurality of conductor segments are positionable to form a substantially complete loop. A first conductor segment of the plurality of conductor segments is electrically isolated from a second conductor segment of the plurality of conductor segments.

Abstract: A margin tester including an identification reader configured to receive an adaptor identifier of an adaptor, an interface configured to connect to a device under test through the adaptor, and one or more processors configured to assess a margin, such as an electrical margin or an optical margin, of a device under test and tag the assessment with the adaptor identifier. Assessing the margin can include assessing the margin based on an expected margin that is predicted or provided based on the adaptor identifier.

Abstract: A test and measurement instrument, including at least one port configured to receive a signal from a device under test (DUT), the signal including a current signal acquired across a magnetic core of the DUT and a voltage signal acquired across the magnetic core of the DUT, and one or more processors. The one or more processors are configured to determine a hysteresis loop based on the current signal and the voltage signal, determine a magnetic flux of the magnetic core based on the voltage signal and the current signal for a number of sample points for each cycle, and determine a maximum magnetic flux for all cycles and a hysteresis loop cycle that corresponds to the maximum magnetic flux. A display configured to display at least one of the hysteresis loop, the signal received from the DUT, and the hysteresis loop cycle that corresponds to the maximum magnetic flux.

Abstract: A test system can include a probe suitable to be coupled between a test measurement device and a device under test (DUT). The probe can include a signal input to receive an active signal from the DUT and a signal output to provide the active signal to the test measurement device. The probe can also include an input ground to connect to the DUT ground and an output ground to connect to the test measurement device ground. A probe ground connection checking device can automatically determine whether the probe ground connections to the DUT ground and test measurement device ground are solid.

Abstract: A system an input to receive a waveform signal, and one or more processors configured to execute code to cause the one or more processors to extract data bursts from the waveform signal, generate corresponding data vectors from the raw data for each data burst, and use machine learning to classify each data burst from the corresponding data vector. A method of classifying a data burst, comprising receiving an input waveform, extracting data bursts from the input waveform, deriving one or more spectral features of the data bursts, generating corresponding data vectors for each data burst from the one or more spectral features, and using machine learning to classify the data bursts from the corresponding data vectors.

Abstract: A calibrated test and measurement cable for connecting one or more devices under test and a test and measurement instrument, including a first port structured to electrically connect to a first signal lane, a second port structured to electrically connect to a second signal lane, a third port structured to electrically connect to a test and measurement instrument, and a multiplexer configured to switch between electrically connecting the first port to the third port and connected the second port to the third port. The first and second signal lanes can be included on the same device under test or different devices under test. An input can receive instructions to operate the multiplexer.

Abstract: A cable structured to be repeatedly connected to a device, each repeated connection causing degradation of the cable, the cable including a condition indicator disposed on the cable and configured to be updated with each successive connection of the cable into the device.

Abstract: A test and measurement device having a signal source, including an impairment generator configured to output an impairment and a waveform synthesizer. The waveform synthesizer receives an input digital signal to be synthesized, receives the impairment, and synthesizes a synthesized digital signal based on the input digital signal and the impairment. The test and measurement instrument also includes a fixed sample rate digital-to-analog converter configured to receive a clock signal and the synthesized digital signal and output an analog signal.

Abstract: A test and measurement instrument, including a memory configured to store a waveform data record; one or more processors, and a display. The one or more processors are configured to receive the waveform data record, determine a measurement value and location for a plurality of occurrences of a measurement event in the waveform data record, detect one or more logical path segments in the plurality of occurrences, and generating a visual representation of each measurement value and overlaying each of the visual representations of each measurement value. The visual representations of each measurement value and/or the one or more logical path segments may be displayed on the display.

Abstract: A method for indicating a probing target for a fabricated electronic circuit including: generating an electronic, three-dimensional model based on manufacturing layout information of a fabricated circuit; obtaining, with a vision system, visual environment information for the fabricated circuit; scaling and orienting the three-dimensional model by a scaler and mapper based on the visual environment information; overlaying the three-dimensional model with the visual environment information to produce a correlated image; obtaining an identification of a desired network node of the fabricated circuit; and indicating a probing target, the probing target corresponding to the desired network node of the fabricated circuit.

Abstract: A test and measurement instrument, comprising a display and one or more processors configured to display a waveform viewing area, receive a selection of a viewing mode. When an overlay viewing mode is selected, display two or more waveforms overlaid in a single graticule in the waveform viewing area, and when a stacked viewing mode is selected, display a first waveform in a first slice having a first graticule in the waveform viewing area and display a second waveform in a second slice having a second graticule below the first slice in the waveform viewing area.

Abstract: A new test system includes a programmed device having an input port for receiving a signal for testing or measuring on the programmed device, and a reprogrammable test accessory having an output coupled to the input port of the programmed device. The reprogrammable test accessory further includes a test port structured to accept one or more test signals from a Device Under Test (DUT), and a reprogrammable processor. The reprogrammable processor may further include reprogrammable standards and protocols, reprogrammable triggers and margin detection, reprogrammable link training, reprogrammable handshaking, and reprogrammable setup and control facilities for either or both of the DUT and the programmed device.

Abstract: A system for verifying signals in electronic circuits that includes a waveform translator and a test-and-measurement instrument. The waveform translator is configured to receive a simulated waveform for a node of a simulated prototype circuit and to translate the simulated waveform into a translated waveform. The test-and-measurement instrument is configured to obtain a measured waveform and to determine a deviation of the measured waveform from the simulated waveform using the translated waveform.

Abstract: A method comprising categorizing nodes of a fabricated circuit as being priority nodes and nodes as being inferior nodes; evaluating a first priority node by automatically designating for verification the first priority node, and ascertaining whether a measured signal from the first priority node meets a pass-fail criterion for the first priority node; evaluating, when the measured signal from the first priority node meets the pass-fail criterion, a second priority node by automatically designating for verification the second priority node, and ascertaining whether a measured signal from the second priority node meets a pass-fail criterion for the second priority node; and evaluating, when the measured signal from the first priority node does not meet the pass-fail criterion, a first inferior node, by automatically designating for verification the first inferior node, and ascertaining whether a measured signal from the first inferior node meets a pass-fail criterion for the first inferior node.

Abstract: A method of securing a probe tip to a device under test (DUT), the method comprising: positioning the probe tip near a test point of the DUT, the probe tip comprising a connection point on a signal-path portion of the probe tip and an attachment tab, the connection point making an electrical connection with the test point of the DUT, the attachment tab extending away from the signal-path portion of the probe tip; applying an adhesive to the DUT through a hole in the attachment tab of the probe tip; and curing the adhesive to secure the probe tip to the DUT.

Abstract: A test and measurement system for analyzing a device under test, including a database configured to store test results related to tests performed with one or more prior devices under test, a receiver to receive new test results about a new device under test, a data analyzer configured to analyze the new test results based on the stored test results, and a health score generator configured to generate a health score for the new device under test based on the analysis from the data analyzer.

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link with a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.