Abstract: A tester interface unit comprising a test hardware module. The test hardware module may have a simple construction, relying on control and/or signal processing in one or more tester instruments to generate or analyze test signals for a device under test. The test hardware module may be disposed within the tester interface unit, providing a short and high integrity signal path length to the device under test. The tester interface unit may include a purge gas chamber and a cooling chamber, with the hardware module penetrate a separator between those chambers, sealing an opening between the purge gas chamber and the cooling chamber. A heat spreader may move heat generated on the portion of the test hardware module in the purge gas chamber to the cooling chamber.

Abstract: An example manipulator for transporting a test head includes: a tower having a base and a track, with the track being vertical relative to the base; an arm to enable support for the test head, with the arm being connected to the track to move the test head vertically relative to the tower; one or more motors to drive movement of the arm along the track; and pneumatic cylinders to control movement of the arm to cause the test head to apply an amount of force to a peripheral device.

Abstract: An example method includes broadcasting periodically, from a computing system, control packets over a network to instrument modules, where a control packet includes data representing sequence numbers of last data packets received from the instrument modules and information based on the sequence numbers, and the control packet includes slots for all of the instrument modules, with each slot containing the data that is specific to one of the instrument modules. The example method also includes receiving, at the computing system and in response to the control packet, via unicast and over the network, an acknowledgement packet from each of the instrument modules, where the acknowledgement packet includes repair information that is based on a broadcast control packet received by the instrument module from the computing system.

Abstract: An example test system includes: multiple channels, where each of the multiple channels is configured to force voltage and to source current; and circuitry to combine current sourced by the multiple channels to produce a combined current for output on a single channel to a device under test (DUT), where each of the multiple channels includes a load sharing resistor to control a contribution of the channel to the combined current.

Abstract: An example method includes: for a component supported by an air bearing, detecting a speed of movement of the component relative to a predefined location, the air bearing generating an air flow to elevate the component relative to a ground plane; and controlling the air bearing based, at least in part, on the speed detected.

Abstract: Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows, the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions.

Abstract: Apparatus and methods for calibrating tester channels of an automated test system. A relay matrix assembly including a plurality of microelectromechanical (MEM) switches may be used to connect a plurality of tester channels to an analyzer calibration instrument rapidly without requiring serial, robotic probing of the test channels. The relay matrix assembly may be constructed on a printed circuit board that can be attached to an interface on the tester. Calibration parameters for the test channels may be calculated from waveforms received through the relay matrix assembly and that have been corrected to remove waveform distortion introduced by the relay matrix assembly. Parameters to correct for distortion in the relay matrix assembly may be measured in advance and stored for use when calibration is to be performed.

Abstract: A testing device for testing a radar device. The testing device may be configured to determine a first frequency difference between a frequency of a first signal or a second signal and a frequency of a third signal based on a first distance value; transmit to the radar device the first signal; receive the second signal from the radar device; transmit to the radar device the third signal at an offset relative to at least one of the first signal and the second signal based on the first frequency difference; and receive from the radar device a fourth signal indicating a second distance value or a second frequency difference between the frequency of the second signal and the frequency of the third signal, determined by the radar device, for comparison with the first distance value or the first frequency difference.

Abstract: Example automatic test equipment (ATE) may include: a device interface board (DIB) on which the DUT is mounted; a system for sending signals to, and receiving signals from, the DUT; and an energy source unit (ESU) to provide current to the DUT via the DIB, where the ESU includes current paths to provide the current, and where the current paths are configured to limit a combined inductance of the current paths.

Abstract: An example test fixture, which interfaces a tester and a unit under test (UUT), includes the following: first electrical contacts that face the tester; second electrical contacts that face the UUT; a substrate made of sections of printed first material, with the first material being electrically non-conductive, and with the substrate being between the first electrical contacts and the second electrical contacts; and structures through the substrate, with the structures including sections of second material, with the second material being electrically conductive, and with at least one of the structures electrically connecting a first electrical contact and a second electrical contact.

Abstract: A test system that enables real-time interactive debugging of a device under test (DUT) using native customer code. A translation module may format, in real time, debug commands, corresponding to a user input, into a format recognizable by instruments in a tester. The user input may be a test program or test instructions written in a high-level programming language. The translation module may translate the user's debug commands into lower-level test instrument commands, based on which the tester may apply control signals to a processor in the DUT to test subsystems of the DUT. A result of the test may be provided to the translation module, which may, in real time, format another debug command, or provide an indication of the result to the user. The translation module may thus enable a user to step-through and modify native customer code in an interactive manner to debug a DUT.

Abstract: A probe for automatic test equipment (ATE) includes: an outer shroud including a course alignment feature configured to receive a target device and to guide the target device into an interior of the outer shroud, where the target device includes exposed electrical leads; and an inner structure that is at least partly inside the outer shroud. The inner structure includes electrical contacts for making an electrical connection to the exposed electrical leads, and also includes a fine alignment feature configured to guide the target device towards the electrical contacts to make the electrical connection.

Abstract: According to some aspects, a system and method for processing messages in a plurality of successive cycles is provided. One such system may include a plurality of first circuits, each first circuit configured to output a message, the plurality of first circuits configured to operate synchronously, a first plurality of buffers, each buffer associated with a respective first circuit and configured to store a message output by the respective first circuit, a communication path configured to receive the plurality of messages from the buffers and to perform aggregation of the messages, thereby generating an aggregated indication, and one or more second circuits. The one or more second circuits are configured to operate synchronously and to receive the aggregated indication, wherein buffers of the first plurality of buffers are configured to store messages from respective first circuits for different times.

Abstract: An example circuit board structure includes: a substrate; and vias that are electrically conductive and that pass through the substrate to enable electrical connection through the circuit board structure. The substrate is thinner, and lengths of the vias are shorter, in first areas of the circuit board structure that deliver first speed signals than in second areas of the circuit board structure that deliver second speed signals and power. The first speed signals have a shorter rise time than the second speed signals.

Abstract: An example process for determining electrical path lengths includes: injecting current into a transmission line having a known capacitance per unit of length; determining a rate of change in voltage on the transmission line in response to the current; determining a capacitance of the transmission line based on the change in voltage; and determining an electrical path length of the transmission line based on the determined capacitance of the transmission line and the known capacitance per unit of length.

Abstract: A probe assembly for capacitive testing electrical connections of a low profile component to a circuit assembly. The probe assembly is configured to reduce coupling of noise signals from the circuit assembly to the capacitive probe. The probe assembly includes a sensing member with a geometry that allows the probe to preferentially couple to test signals from the pins of a component under test rather than conductive structures on the circuit assembly, such as pads, and signal traces to which those pins are attached. The sensing member may be a vertical capacitive sense plate such that coupling is to an edge of the plate. The sensing member alternatively may be a horizontal capacitive sense plate with an active area of the probe surrounded by an isolation ring. Measurements made with such capacitive probes may provide test measurements that yield a reliable discrimination between a properly attached pin and an open pin.

Abstract: A storage device test slot includes a housing. The housing defines a test compartment for receiving a storage device for testing. One or more tuned mass dampers are connected to the housing. The one or more tuned mass dampers are configured to inhibit vibration of the housing at one or more predetermined frequencies.

Abstract: An example apparatus for interfacing between automatic test equipment (ATE) and a device under test (DUT) includes: multiple stages arranged in sequence between the ATE and the DUT, where each of the multiple stages includes a driver, at least two of the multiple stages each includes a filter, each filter is arranged between two drivers, and each filter is configured to reduce jitter produced by a preceding driver in a signal transmitted between the ATE and the DUT.

Abstract: An example test system includes: a heating mechanism; a cooling mechanism; an instrument module having one or more interfaces to receive signals from a device under test (DUT), where the instrument module includes one or more electrical components to affect the signals, where the instrument module is between the heating mechanism and the cooling mechanism, and where the heating mechanism and the cooling mechanism are each configured to operate to maintain the instrument module within a target temperature range.

Abstract: An example method includes: obtaining sinusoidal signals comprising components of a first time-domain signal; shifting phases of the sinusoidal signals by amounts corresponding to a specified time-shift to produce phase-shifted signals, and converting the phase-shifted signals to the time domain to produce time-shifted signals. The shifting may be performed to more closely align an envelope of the first time-domain signal with an envelope of a second time-domain signal.