Patents Assigned to Teradyne, Inc.
  • Programmable test instrument
    Patent number: 9759772
    Abstract: In general, a test instrument includes a first processing system that is programmable to run one or more test programs to test a device interfaced to the test instrument, and that is programmed to control operation of the test instrument, a second processing system that is dedicated to device testing, the second processing system being programmable to run one or more test programs to test the device, and programmable logic configured to act as an interface between the test instrument and the device, the programmable logic being configurable to perform one or more tests on the device. The first processing system and the second processing system are programmable to access the device via the programmable logic.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 12, 2017
    Assignee: Teradyne, Inc.
    Inventors: David Kaushansky, Lloyd K. Frick, Stephen J. Bourassa, David Vandervalk, Michael Thomas Fluet, Michael Francis McGoldrick
  • Front end module for automatic test equipment
    Patent number: 9755766
    Abstract: Example automatic test equipment (ATE) includes: a test instrument for outputting test signals to test a device under test (DUT), and for receiving output signals from the DUT, with the test instrument including a front-end module, and with the front-end module including internal circuitry for performing functions relating to the DUT; and external circuitry for performing the functions relative to the DUT via the test instrument, with the external circuitry being external to the front-end module and being shared among multiple front-end modules or channels of the test instrument. The test instrument is configurable to use either (i) the internal circuitry, (ii) the external circuitry, or (iii) a combination of circuits in the internal circuitry and the external circuitry to perform the functions.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: September 5, 2017
    Assignee: Teradyne, Inc.
    Inventors: Brian C. Wadell, Daniel Rosenthal
  • AUTOMATIC TEST SYSTEM WITH FOCUSED TEST HARDWARE
    Publication number: 20170212164
    Abstract: A tester interface unit comprising a test hardware module. The test hardware module may have a simple construction, relying on control and/or signal processing in one or more tester instruments to generate or analyze test signals for a device under test. The test hardware module may be disposed within the tester interface unit, providing a short and high integrity signal path length to the device under test. The tester interface unit may include a purge gas chamber and a cooling chamber, with the hardware module penetrate a separator between those chambers, sealing an opening between the purge gas chamber and the cooling chamber. A heat spreader may move heat generated on the portion of the test hardware module in the purge gas chamber to the cooling chamber.
    Type: Application
    Filed: January 26, 2016
    Publication date: July 27, 2017
    Applicant: Teradyne, Inc.
    Inventors: Michael A. Caradonna, Daniel A. Derringer, Stephen R. Wilkinson
  • Bus interface system for interfacing to different buses
    Patent number: 9672127
    Abstract: An example test system includes a bus interface to connect to a bus of a computer system; and test instruments to perform one or more test operations on a UUT, where the test instruments connect to the bus interface to enable communication between the computer system and the test instruments via the bus interface. At least one test instrument includes: ports to which the UUT is connectable, with each of the ports interfacing to a corresponding peripheral bus supported by the at least one test instrument; circuits to connect the bus interface to the peripheral buses, with each circuit being configured to convert between a bus interface protocol run on the bus interface and a peripheral bus protocol run on a peripheral bus; and a switch to identify a target circuit of the circuits, with the switch to direct communications between the computer system and the target circuit.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: June 6, 2017
    Assignee: Teradyne, Inc.
    Inventors: Michael Thomas Fluet, Peter Hansen, Pavel Gilenberg
  • Method and apparatus for testing electrical connections on a printed circuit board
    Patent number: 9638742
    Abstract: A test system and method for identifying open and shorted connections on a printed circuit board (PCB). An integrated circuit (IC) unit on the PCB is configured to generate a test signal on an output pin connected to a test pin on a second device, connector, or socket on the PCB. For a connection, the test signal is capacitively coupled to a detector plate proximal the second device. Based on the signal coupled to the detector, time domain analysis is performed on the coupled signal to determine if the test pin has a good connection to the PCB or if the pin is open or shorted. Analysis may include cross-correlating the coupled signal with a learned signal obtained from a known “good” PCB. The test pin may pass the test if the cross-correlation is within a specified threshold window. If the test fails, additional tests may be performed to troubleshoot the cause of the testing failure.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: May 2, 2017
    Assignee: Teradyne, Inc.
    Inventor: Anthony J. Suto
  • MANIPULATOR IN AUTOMATIC TEST EQUIPMENT
    Publication number: 20170115327
    Abstract: An example manipulator for transporting a test head includes: a tower having a base and a track, with the track being vertical relative to the base; an arm to enable support for the test head, with the arm being connected to the track to move the test head vertically relative to the tower; one or more motors to drive movement of the arm along the track; and pneumatic cylinders to control movement of the arm to cause the test head to apply an amount of force to a peripheral device.
    Type: Application
    Filed: October 23, 2015
    Publication date: April 27, 2017
    Applicant: Teradyne, Inc.
    Inventors: Gary Fowler, Vladimir Vayner
  • Structure for transmitting signals in an application space between a device under test and test electronics
    Patent number: 9594114
    Abstract: An example structure for transmitting signals in an application space between a device under test (DUT) and test electronics includes: a circuit board that is part of an application space between test electronics and a device under test (DUT); and a coaxial structure to pass signals along electrical pathways between the test electronics and the DUT. The coaxial structure includes a signal line at least partially surrounded by a return line.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: March 14, 2017
    Assignee: Teradyne, Inc.
    Inventor: Roger Allen Sinsheimer
  • CONDUCTIVE TEMPERATURE CONTROL
    Publication number: 20170059635
    Abstract: A test system includes a transporter having test sockets, where each test socket is configured to receive a device to be tested by the test system, and each test socket includes an element that is controllable to change a temperature of a device in the test socket through thermal conduction. The test system includes a test rack comprising slots. The transporter is configured for movement into, and out of, a slot of the test rack to test devices in the test sockets.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Applicant: TERADYNE INC.
    Inventors: Shant Orchanian, Valquirio N. Carvalho, Philip Campbell, Matthew David Pollack
  • High speed data transfer using calibrated, single-clock source synchronous serializer-deserializer protocol
    Patent number: 9577818
    Abstract: An electronic system, comprising a first semiconductor device, a second semiconductor device, a clock circuit, and a plurality of independently adjustable calibration circuits connected in each of the plurality of serial data paths. The first semiconductor device may comprise a plurality of Serializer-Deserializer interfaces. The second semiconductor device may comprise a plurality of serial data interfaces coupled to the plurality of Serializer-Deserializer interfaces to provide a plurality of serial data paths between the first semiconductor device and the second semiconductor device. The plurality of Serializer-Deserializer interfaces and the plurality of serial data interfaces may be clocked from a clock signal derived from the clock circuit. The plurality of independently adjustable calibration circuits may be configured to compensate for timing differences across the plurality of serial data paths.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: February 21, 2017
    Assignee: Teradyne, Inc.
    Inventor: George W. Conner
  • MEM RELAY ASSEMBLY FOR CALIBRATING AUTOMATED TEST EQUIPMENT
    Publication number: 20170038453
    Abstract: Apparatus and methods for calibrating tester channels of an automated test system are described. A relay matrix assembly comprising a plurality of microelectromechanical (MEM) switches may be used to connect a plurality of tester channels to analyzer calibration instrument rapidly without requiring serial, robotic probing of the test channels. The relay matrix assembly may be constructed on a printed circuit board that can be attached to an interface on the tester. Calibration parameters for the test channels may be calculated from waveforms received through the relay matrix assembly and that have been corrected to remove waveform distortion introduced by the relay matrix assembly. Parameters to correct for distortion in the relay matrix assembly may be measured in advance and stored for use when calibration is to be performed.
    Type: Application
    Filed: August 5, 2015
    Publication date: February 9, 2017
    Applicant: Teradyne, Inc.
    Inventor: Alan Hussey
  • Deskew of rising and falling signal edges
    Patent number: 9503065
    Abstract: Example circuitry includes: a first sampling circuit configured to operate based on a first clock signal, to receive data, and to sample the data, where the first clock signal is calibrated to compensate for a first timing error in a rising edge of the data; a second sampling circuit configured to operate based on a second clock signal, to receive the data, and to sample the data, where the second first clock signal is calibrated to compensate for a second timing error in a falling edge of the data; and a third sampling circuit to receive the data and a third clock signal, to sample the data based on the third clock signal to produce sampled data, and to control an output of the circuitry based on the sampled data to be either an output of the first sampling circuit or an output of the second sampling circuit.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 22, 2016
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Antonie van der Wagt, Ron Sartschev, Bradley A Phillips
  • Test instrument having a configurable interface
    Patent number: 9470759
    Abstract: In general, a test instrument includes a processing system programmed to control operation of the test instrument, including communication with a control system, and programmed to run one or more test programs to test a device interfaced to the test instrument, the processing system including multiple processing devices, and a configurable interface, through which communications are exchanged with the device interfaced to the test instrument, the configurable interface including physical ports, to which different configurations are assignable.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: October 18, 2016
    Assignee: Teradyne, Inc.
    Inventors: Stephen J. Bourassa, Michael Francis McGoldrick, David Kaushansky, Michael Thomas Fluet
  • Electronic assembly test system
    Patent number: 9459312
    Abstract: An example system for testing electronic assemblies (EAs) may include carriers for holding EAs and slots for testing at least some of the EAs in parallel. Each slot may be configured to receive a corresponding carrier containing an EA and to test the EA. An example carrier in the system may include a first part and a second part. At least one of the first part and the second part include a first structure, and the first structure is movable to enable electrical connection between an EA and an electrical connector.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: October 4, 2016
    Assignee: Teradyne, Inc.
    Inventors: John Joseph Arena, Anthony J. Suto
  • Circuitry to protect a test instrument
    Patent number: 9448274
    Abstract: Controlling a test instrument may include: determining a first value corresponding to power output by the test instrument; determining a second value based on the first value, where the second value corresponds to an amount of energy consumed by the test instrument; and placing at least part of the test instrument in a high-impedance state when the second value exceeds a threshold.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: September 20, 2016
    Assignee: Teradyne, Inc.
    Inventors: Douglas W. Pounds, Charles J. Carline
  • ATE to detect signal characteristics of a DUT
    Patent number: 9442148
    Abstract: Automatic test equipment (ATE) includes: a circuit to split a stimulus signal, which contains both deterministic and random (noise floor) spectra contents, from a device under test (DUT) into a first signal and a second signal; a first channel to receive the first signal, where the first channel adds a first noise floor to the first signal to produce a first channel signal; a second channel to receive the second signal, where the second channel adds a second noise floor to the second signal to produce a second channel signal, the first noise floor, the second noise floor and the DUT noise floor all being mutually uncorrelated; and processing logic to: estimate a first power of the deterministic stimulus signal, and estimate a second total power based on the first channel signal and the second channel signal.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: September 13, 2016
    Assignee: Teradyne, Inc.
    Inventor: Ka Ho Colin Chow
  • Interconnect for transmitting signals between a device and a tester
    Patent number: 9435855
    Abstract: A system includes: a circuit board including electrical elements arranged at a first pitch; a wafer including contacts arranged at a second pitch, where the second pitch is less than the first pitch; and an interconnect including additively-manufactured electrical conduits that are part of an electrical pathway between the electrical elements and the contacts, where the additively-manufactured electrical conduits include electrically-conductive material.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 6, 2016
    Assignee: Teradyne, Inc.
    Inventors: David Walter Lewinnek, Roger Allen Sinsheimer, Luis Antonio Valiente, Craig Anthony DiPalo
  • VIRTUAL DISTANCE TEST TECHNIQUES FOR RADAR APPLICATIONS
    Publication number: 20160245900
    Abstract: A testing device for testing a radar device. The testing device may be configured to determine a first frequency difference between a frequency of a first signal or a second signal and a frequency of a third signal based on a first distance value; transmit to the radar device the first signal; receive the second signal from the radar device; transmit to the radar device the third signal at an offset relative to at least one of the first signal and the second signal based on the first frequency difference; and receive from the radar device a fourth signal indicating a second distance value or a second frequency difference between the frequency of the second signal and the frequency of the third signal, determined by the radar device, for comparison with the first distance value or the first frequency difference.
    Type: Application
    Filed: February 19, 2015
    Publication date: August 25, 2016
    Applicant: Teradyne, Inc.
    Inventors: Jeorge S. Hurtarte, Daniel A. Rosenthal
  • HIGH SPEED DATA TRANSFER USING CALIBRATED, SINGLE-CLOCK SOURCE SYNCHRONOUS SERIALIZER-DESERIALIZER PROTOCOL
    Publication number: 20160227004
    Abstract: An electronic system, comprising a first semiconductor device, a second semiconductor device, a clock circuit, and a plurality of independently adjustable calibration circuits connected in each of the plurality of serial data paths. The first semiconductor device may comprise a plurality of Serializer-Deserializer interfaces. The second semiconductor device may comprise a plurality of serial data interfaces coupled to the plurality of Serializer-Deserializer interfaces to provide a plurality of serial data paths between the first semiconductor device and the second semiconductor device. The plurality of Serializer-Deserializer interfaces and the plurality of serial data interfaces may be clocked from a clock signal derived from the clock circuit. The plurality of independently adjustable calibration circuits may be configured to compensate for timing differences across the plurality of serial data paths.
    Type: Application
    Filed: February 4, 2015
    Publication date: August 4, 2016
    Applicant: Teradyne, Inc.
    Inventor: George W. Conner
  • Edge generator-based phase locked loop reference clock generator for automated test system
    Patent number: 9397670
    Abstract: An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a delay input. The edge generator may produce at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted. The phase locked loop may comprise a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency. The delay adjustment circuit may comprise an accumulator that may increase in value by a programmed amount for each cycle of the clock.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: July 19, 2016
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Jeffrey Wade Sanders, Thomas Aquinas Repucci, Ronald A. Sartschev
  • GRASPING GRIPPER
    Publication number: 20160089793
    Abstract: An example gripper may include: a base; two or more fingers attached to the base, with each finger being movable towards, and away from, one or more others of the fingers; and one or more ports at the base or at one or more of the fingers to provide suction through a vacuum.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 31, 2016
    Applicant: TERADYNE, INC.
    Inventor: Eric L. Truebenbach