Abstract: A fully depleted SOI device includes a semiconductor substrate and a conductive well of a first conductivity type formed in a principal surface of the semiconductor substrate. An insulating layer is formed along the principal surface of the semiconductor substrate and extends across the conductive well. A transistor is formed on the insulating layer such that the insulating layer is interposed between the transistor and the semiconductor substrate, with the transistor including source and drain regions of the first conductivity type formed on the insulating layer, a channel region of a second conductivity type formed on the insulating layer and aligned over the conductive well, and a gate electrode aligned over the channel region. A metal contact is connected to the conductive well for applying a reverse bias potential to the transistor.

Abstract: The present invention discloses a thermally enhanced Thin Quad Flatpack (TQFP) integrated circuit package. The invention's thermally enhanced TQFP is sufficiently thin for use in small form factor electronic systems such as Personal Computer Memory Card International Association (PCMCIA) Type III (10.5 millimeter) disk drives, modules and cards. Furthermore, the invention's thermally enhanced TQFP is reliable and has a significantly reduced thermal resistivity. Moreover, the invention does not require expensive tooling of the leadframe. Accordingly, the invention's thermally enhanced TQFP's production cost is far below that of comparable thermally enhanced packages. The invention's thermally enhanced TQFP comprises a leadframe having a number of leads. A heat spreader is attached to the bottom of the leadframe. The heat spreader extends to, and is in thermal contact with, the leads of the leadframe. This permits a larger surface for heat dissipation.

Abstract: A circuit and method for providing a plurality of voltage regulators whose outputs are constant for ranges of different external voltages are disclosed. The voltage regulators are made to be adaptable to two different ranges of external voltages through use of a master-slice technique. Furthermore, in a first voltage regulator, the supply current capability of the regulator is significantly increased under very low external voltage conditions. In a second voltage regulator, the voltage level on any node of the regulator does not exceed a voltage level that is too high, yet still sinks most of its current from the external power supply. A third voltage regulator is able to charge and discharge its output voltage so that it will maintain at a constant level. Finally, a fourth voltage regulator is optimized to reduce dielectric leakage.

Abstract: The present invention configures a control strategy and a process model to calculate a setting of a machine. The present invention adjusts the process model in accordance with an analysis of the setting to control the machine.

Abstract: The present invention provides a method of ameliorating the effects of misalignment between modulator, and a system using the same. The individual modulator elements are positioned such that a portion of the image produced is generated by both elements. The contribution to the combined output made by each element varies across the overlapped region, with each element making a small contribution to the pixels in the overlapped region at one end and a large contribution to pixels in the overlapped region at the other end. Because the overlapping output regions of the modulators collectively form a portion of the image, any alignment error is effectively spread over the entire overlapped region and is much less noticeable.

Abstract: The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array.Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

Abstract: A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.

Abstract: Waveguide sensors are formed on a chip package which contains at least one source and at least one detector. Simple waveguide elements are mounted on the chip. Waveguide defining elements can also be formed integrally with the chip package so that simple waveguide bodies can be inserted or removed. Various geometries of source, reference detector, and sensing detector can be produced. A liquid waveguide sensor is formed by filling a waveguide channel with a liquid reagent.

Abstract: A lead frame for a semiconductor IC device has a pair of common elongated leads and first and second groups of slender leads arranged on opposite sides of the common elongated leads and generally extending transverse to the common elongated leads. The common elongated leads have as their integral parts slender leads extending therefrom generally transverse thereto and substantially linear extensions from both ends of the common elongated leads. The linear extensions serve to firmly support a semiconductor chip to be packaged along with parts of the leads. The common elongated leads may further have as their integral parts projections extending from their sides for enhancement of the heat dissipation capability. A semiconductor chip may have bonding pads arranged thereon such that bonding wires and the common elongated leads do not cross each other for electrical connection between the common elongated leads and bonding pads of the semiconductor chip.

Abstract: The invention discloses a high density semiconductor package. Two semiconductor chips are each affixed on a corresponding one of two lead frames. The semiconductor chips and the lead frames are encapsulated, wherein only a portion of the leads of the lead frames protrudes and extends from the package.

Abstract: A voltage generating circuit in a semiconductor integrated circuit driven by two sorts of power supply voltages, includes a unit for generating plural sorts of signals; a unit for selecting one of the plural sorts of signals in response to an operation mode of the semiconductor integrated circuit; and a pumping unit for producing either a first predetermined voltage higher than the high power supply voltage among the two sorts of power supply voltages, or a second predetermined voltage lower than the low power supply voltage by a pumping operation based upon the signal selected by the selecting unit.

Abstract: A method of fabricating a double level metal (DLM) anode plate for use in a field emission device comprises the steps of providing a transparent substrate 82 having an active region 58 and a bus region 62. Then providing electrically conductive regions 50 on the surface. The conductive regions 50 span the active region 58 and the bus region 62. Next, the surface is coated with an electrically insulating material 94 and then the electrically insulating material 94 is removed from selected portions of the bus region 62, the active region 58, and upper portions of the transparent substrate 82. A first bus 52 is provided for electrically connecting a first series of the conductive regions, a second bus 54 is provided for electrically connecting a second series of the conductive regions, and a third bus 56 is provided for electrically connecting a third series of the conductive regions. Luminescent material of a first color 88.sub.R is applied to the first series of conductive regions 50.sub.

Abstract: In a semiconductor device having conductive paths for electrically coupling a substrate surface with a second conductive/wiring layer, the substrate and the second conductive layer having a first conductive layer therebetween, a second insulating layer separating the first and the second conductive/wiring layers is replaced by a process for forming a protective covering over the patterned and etched first conductive layer. The second conductive layer will provide an electrical contact with the exposed conducting material in the contact holes without the critical patterning and etching process steps typically required when the second insulating layer is formed.

Abstract: A lead frame for a semiconductor IC device has a pair of common elongated leads and first and second groups of slender leads arranged on opposite sides of the common elongated leads and generally extending transverse to the common elongated leads. The common elongated leads have as their integral parts slender leads extending therefrom generally transverse thereto and substantially linear extensions from both ends of the common elongated leads. The linear extensions serve to firmly support a semiconductor chip to be packaged along with parts of the leads. The common elongated leads may further have as their integral parts projections extending from their sides for enhancement of the heat dissipation capability. A semiconductor chip may have bonding pads arranged thereon such that bonding wires and the common elongated leads do not cross each other for electrical connection between the common elongated leads and bonding pads of the semiconductor chip.

Abstract: A method of fabricating an anode plate 80 for use in a field emission device. The method comprises the steps of providing a substantially transparent substrate 88 having spaced-apart, electrically conductive regions 50 on a surface thereof, then coating the anode plate with a substantially opaque material 86. The opaque material 86 is removed from the surface of the conductive regions 50 in the active area 58, and from selected areas 60 of the interconnect portion of the conductive regions 50. A first bus 52 is provided for electrically connecting a first series 50.sub.R of the conductive regions 50, a second bus 54 is provided for electrically connecting a second series 50.sub.G of the conductive regions 50, and a third bus 56 is provided for electrically connecting a third series 50.sub.B of the conductive regions 50. Luminescent material of a first color 84.sub.R is applied to the first series of conductive regions 50.sub.R, luminescent material of a second color 84.sub.

Abstract: A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.

Abstract: A field emission display apparatus comprised of an emitter plate 2 having a plurality of column conductors 9 intersecting a plurality of row conductors 6, and electron emitters 5 at the intersection of each of the row and column conductors. An anode plate 62 is adjacent to the emitter plate 2, the anode plate 62 comprising conductive stripes 90 which are alternately covered by material luminescing in the three primary colors. The conductive stripes 90 covered by the same luminescent material are electrically interconnected to form comb-like structures corresponding to each of the colors. The anode plate 62 contains an active region 58. The conductive stripes 90 have a first width W.sub.7 within the active region 58 and a second different width W.sub.8 outside of the active region 58.

Abstract: A preferred embodiment of this invention comprises a thin unreactive film (e.g. platinum 36) contacting a high-dielectric-constant material (e.g. barium strontium titanate 38) to an electrode. The thin unreactive film provides a stable conductive interface between the high-dielectric-constant material layer and the electrode base (e.g palladium 34). As opposed to a standard thin-film layer, the thin unreactive film is generally less than 50 nm thick, preferably less than 35 nm thick, more preferably between 5 nm and 25 nm thick, and most preferably between 10 nm and 20 nm thick. A thin unreactive film can benefit from the advantages of the materials used while avoiding or minimizing many of their disadvantages. A thin unreactive film would generally be substantially less expensive than a standard thin-film layer since much less material can be used while not significantly affecting the surface area of the electrode in contact with the HDC material.

Abstract: A method of fabricating an anode plate 40 having a multiplicity of grooves 50 for use in a field emission flat panel display device comprises the steps of providing a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device; etching a plurality of grooves 50 in the surface of the substrate in the spaces between the stripes 46; and then applying phosphor material 48.sub.R, 48.sub.G and 48.sub.B over the stripes 46. In one embodiment, a plurality of grooves 50', having generally vertical sidewalls, are formed in the upper surface of planar substrate 42' at the interstices of conductors 46. In a second embodiment, a plurality of grooves 50", having generally curved sidewalls, are formed in the upper surface of planar substrate 42' at the interstices of conductors 46'.

Abstract: A high voltage transistor includes a semiconductor-on-insulator (SOI) region in which a source and a channel are formed. A drain drift region is further formed partly in the SOI region and partly in the bulk silicon region beyond SOI and a gate is coupled to said SOI channel.