Patents Assigned to Texas Instruments Inc.
  • Transistor design self-aligned to contact
    Publication number: 20070059908
    Abstract: The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one aspect, the method of manufacturing a transistor device includes providing a gate structure (140) over a substrate (110). An insulating layer (310) is formed over the gate structure (140), and openings (710) to the substrate (110) are formed therein, thereby removing a portion of the gate structure (140). The openings (710) are filled with a conductor (1410), thereby forming an interconnect (1510).
    Type: Application
    Filed: September 14, 2005
    Publication date: March 15, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Andrew Marshall, Tito Gelsomini, Harvey Davis
  • Method to obtain uniform nitrogen profile in gate dielectrics
    Publication number: 20070054455
    Abstract: The present invention provides, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160, 165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.
    Type: Application
    Filed: September 12, 2005
    Publication date: March 8, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Ajith Varghese, Reima Laaksonen, Terrence Riley
  • Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor
    Publication number: 20070045732
    Abstract: The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).
    Type: Application
    Filed: August 3, 2005
    Publication date: March 1, 2007
    Applicant: Texas Instruments Inc.
    Inventors: John Lin, Tony Phan, Philip Hower, William Loftin, Martin Mollat
  • A Modular Graphics Stack
    Publication number: 20070040787
    Abstract: A system is provided that includes a Liquid Crystal Display (LCD) panel and an LCD controller coupled to the LCD panel. The system also includes a processor coupled to the LCD controller and a memory coupled to the processor. The memory stores a modular graphics stack that provides images and configuration parameters to the LCD controller. The modular graphics stack has a window manager layer, a display driver layer, and an LCD controller hardware abstraction layer (HAL).
    Type: Application
    Filed: August 17, 2006
    Publication date: February 22, 2007
    Applicant: TEXAS INSTRUMENTS, INC.
    Inventor: Nakshatra Saha
  • Modular Graphics Stack With Video Support
    Publication number: 20070040788
    Abstract: A system is provided that includes a Liquid Crystal Display (LCD) panel and an LCD controller coupled to the LCD panel. The system also includes a processor coupled to the LCD controller and a memory coupled to the processor. The memory stores a modular graphics stack that provides images and configuration parameters to the LCD controller. The modular graphics stack has a window manager layer and a display driver layer.
    Type: Application
    Filed: August 17, 2006
    Publication date: February 22, 2007
    Applicant: TEXAS INSTRUMENTS, INC.
    Inventor: Nakshatra Saha
  • Detecting endpoint using luminescence in the fabrication of a microelectronics device
    Publication number: 20070042509
    Abstract: The present invention provides a method of detecting an endpoint of the removal of a material from a microelectronics substrate. This embodiment includes removing at least a portion of an overlying material 210 located over a luminescent layer 215 that is located over a microelectronics substrate 220 and using luminescence emission 240 to determine an endpoint of the removal of the overlying material 210.
    Type: Application
    Filed: August 18, 2005
    Publication date: February 22, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Jingqiu Chen, Yanghua He, Neal Murphy
  • Formation of uniform silicate gate dielectrics
    Publication number: 20070042555
    Abstract: The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one nonmetallic element over a substrate (110). The metal source layer (210) is formed having a composition rich in the metal. A dielectric layer (310) comprising the metal is formed over the metal source layer (210).
    Type: Application
    Filed: August 17, 2005
    Publication date: February 22, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Hiroaki Niimi, Luigi Colombo, James Chambers
  • Process for manufacturing dual work function metal gates in a microelectronics device
    Publication number: 20070037343
    Abstract: The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.
    Type: Application
    Filed: August 10, 2005
    Publication date: February 15, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Luigi Colombo, James Chambers, Mark Visokay
  • Method for removing photoresist using a thermal bake in the presence of hydrogen and a semiconductor device manufactured using the same
    Publication number: 20070037357
    Abstract: The present invention provides a method for removing photoresist, and a method for manufacturing a semiconductor device. The method for removing photoresist, without limitation, may include subjecting a photoresist layer (210) located over a substrate (110) to a thermal bake (410) in the presence of hydrogen, and then removing the photoresist layer (210).
    Type: Application
    Filed: August 11, 2005
    Publication date: February 15, 2007
    Applicant: Texas Instruments Inc.
    Inventor: Donald Culp
  • Semiconductor device having a gate electrode material feature located adjacent a gate width side of its gate electrode and a method of manufacture therefor
    Publication number: 20070034969
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and an integrated circuit including the same. The semiconductor device (300), without limitation, may include a gate electrode (320) having a gate length (l) and a gate width (w) located over a substrate (310) and a gate electrode material feature (330) located adjacent a gate width (w) side of the gate electrode (320). The semiconductor device (300) may further include a silicide region (350) located over the substrate (310) proximate a side of the gate electrode (320), the gate electrode material feature (330) breaking the silicided region (350) into multiple silicide portions (353, 355, 358).
    Type: Application
    Filed: August 12, 2005
    Publication date: February 15, 2007
    Applicant: Texas Instruments Inc.
    Inventor: Dening Wang
  • Dielectric isolated body biasing of silicon on insulator
    Publication number: 20070026584
    Abstract: The present invention provides, in one aspect, a microelectronics device 100 that includes a silicon on insulator (SOI) region 110 located over a microelectronics substrate 115. The SOI region 110 comprises a first dielectric layer 120 located over the microelectronics substrate 115, a biasing layer 125 located over the first dielectric layer 120, and a second dielectric layer 130 located over the biasing layer 125. An active region 135 is located over the SOI region 110. Contact plugs 140 extend through the active region 135 and within the SOI region 110. The present invention also includes a method for making the microelectronics device 100.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 1, 2007
    Applicant: Texas Instruments Inc.
    Inventor: Andrew Marshall
  • DISTRIBUTED HIGH VOLTAGE JFET
    Publication number: 20070012958
    Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.
    Type: Application
    Filed: September 22, 2006
    Publication date: January 18, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Philip Hower, David Walch, John Lin, Steven Merchant
  • Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing
    Patent number: 7163877
    Abstract: A method and system for modifying a gate dielectric stack by exposure to a plasma. The method includes providing the gate dielectric stack having a high-k layer formed on a substrate, generating a plasma from a process gas containing an inert gas and one of an oxygen-containing gas or a nitrogen-containing gas, where the process gas pressure is selected to control the amount of neutral radicals relative to the amount of ionic radicals in the plasma, and modifying the gate dielectric stack by exposing the stack to the plasma.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: January 16, 2007
    Assignees: Tokyo Electron Limited, Texas Instruments, Inc.
    Inventors: Hiroaki Niimi, Luigi Colombo, Koji Shimomura, Takuya Sugawara, Tatsuo Matsudo
  • Novel gate sidewall spacer and method of manufacture therefor
    Publication number: 20070004156
    Abstract: The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a gate dielectric layer (413, 423) and a gate electrode layer (418, 428) over a substrate (310), and forming a gate sidewall spacer (610, 630) along one or more sidewalls of the gate dielectric layer (413, 423) and the gate electrode layer (418, 428) using a plasma enhanced chemical vapor deposition process, and forming different hydrogen concentration in NMOS and PMOS sidewall spacers (610, 630) using a local hydrogen treatment (LHT) method.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 4, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Richard P. Rouse, Shashank S. Ekbote, Haowen Bu
  • Metal oxide semiconductor (MOS) device having both an accumulation and a enhancement mode transistor device on a similar substrate and a method of manufacture therefor
    Publication number: 20060286759
    Abstract: The present invention provides a metal oxide semiconductor (MOS) device, a method of manufacture therefore, and an integrated circuit including the same. The metal oxide semiconductor (MOS) device (100), without limitation, may include a first accumulation mode transistor device (120, 160) located over or in a substrate (110), as well as a second enhancement mode transistor (140, 180) device located over or in the substrate (110).
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Applicant: Texas Instruments, Inc.
    Inventors: Weize Xiong, Rinn Cleavelin
  • Static random-access memory having reduced bit line precharge voltage and method of operating the same
    Publication number: 20060274587
    Abstract: A bit line precharge circuit, a method of precharging a bit line and an SRAM device incorporating the circuit or the method. In one embodiment, the bit line precharge circuit includes: (1) a word line driver coupled to word lines of the SRAM array and configured to operate at a word line driver voltage and (2) a bit line precharge circuit coupled to bit lines of the SRAM array and configured to precharge the bit lines to a precharge voltage substantially lower than the word line driver voltage.
    Type: Application
    Filed: June 2, 2005
    Publication date: December 7, 2006
    Applicant: Texas Instruments Inc.
    Inventor: Theodore Houston
  • Novel method for manufacturing a semiconductor device containing metal silicide regions
    Publication number: 20060258091
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).
    Type: Application
    Filed: May 12, 2005
    Publication date: November 16, 2006
    Applicant: Texas Instruments Inc.
    Inventors: Juanita DeLoach, Lindsey Hall, Lance Robertson, Jiong-Ping Lu, Donald Miles
  • Method for forming fully silicided gates and devices obtained thereof
    Publication number: 20060258156
    Abstract: A method for manufacturing fully silicided (FUSI) gates and devices, in particular MOSFET devices, is described. The method includes deposition a metal layer over a semiconductor layer of a gate stack, providing a first thermal budget to allow a partial silicidation of the semiconductor layer, selectively removing a remaining unreacted metal layer, and providing a second thermal budget to allow a full silicidation of the semiconductor layer. As a result, the silicide phase can be effectively controlled.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicants: Interuniversitair Microelektronica Centrum (IMEC), Texas Instruments Inc.
    Inventor: Jorge Kittl
  • Distributed element generator, method of generating distributed elements and an electronic design automation tool employing the same
    Publication number: 20060259883
    Abstract: The present invention provides a distributed element generator for use with an electronic design automation tool. In one embodiment, the distributed element generator includes a parasitic element extractor configured to identify parasitic elements associated with a passive integrated circuit device having a surrounding layout environment. Additionally, the distributed element generator also includes a distributed parameter allocator coupled to the parasitic element extractor and configured to provide a distributed model of the passive integrated circuit device and allocate the parasitic elements within the distributed model based on the surrounding layout environment.
    Type: Application
    Filed: May 10, 2005
    Publication date: November 16, 2006
    Applicant: Texas Instruments Inc.
    Inventors: Isaac Cohen, Sergey Komarov
  • Method for testing analog and mixed-signal circuits using functionally related excitations and functionally related measurements
    Patent number: 7129734
    Abstract: A method for testing a circuit includes determining at least one performance characteristic of the circuit based on a functional relationship between excitation signals or on a functional relationship between measurement devices. The method is implemented either as a part of a built-in self test circuit of an integrated circuit or for production testing.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: October 31, 2006
    Assignees: Iowa State University Research Foundation, Inc., Texas Instruments, Inc.
    Inventors: Randall Geiger, Kumar Parthasarathy, Degang Chen, Le Jin, Turker Kuyel