Abstract: Disclosed is an optical component, which comprises a prism element adjacent to a lens element, where the two elements are separated by a small air gap. In disclosed embodiments, the elements have adjacent and parallel surfaces which are substantially planar and which, with the small air gap, operate through Total Internal Reflection (“TIR”) to direct light beams that strike the planar surfaces. Light beams that strike at less than the critical angle are internally reflected, while light beams which strike at greater than the critical angle pass through. The TIR surfaces thereby separate the desired optical signals from the spurious ones. The combined TIR prism lens operates as a single and integrated component which directs desired light beams to a reflective optical processing element such as a Spatial Light Modulator and which focuses the processed light beams as they leave the combined TIR prism lens.

Abstract: A circuit and method are presented for detecting a fault in a magneto-resistive head (18). The circuit includes a bias circuit (50) to produce a bias voltage across the head (18) and a pair of resistors (68,70) in series with the head (18) connected to the bias circuit (50) to carry a current (IVMR) from the bias circuit (50) in common with the head. A circuit (102,102′) is provided to determine a ratio of a voltage across the head (18) with respect to a voltage across the head (18) and the pair of resistors (68,70), and a circuit (104,106,104′,106′) is provided for indicating a fault if the ratio falls outside a predetermined range.

Abstract: A switched power supply (40) has a pulse width modulator to adjust a pulse width that controls the output voltage (104). The width modulator includes a comparator (66) that compares a signal (104) indicating a value of the power supply to a ramp wave (69). An output of the comparator (66) is a signal containing a time width proportional to the output of the power supply. Additionally, a first comparator (90) compares the output voltage (42) to a first reference voltage (94). When the output voltage (42) exceeds the first reference voltage (94), the first comparator (90) changes state. A second comparator (88) compares the output voltage (42) to a second reference voltage (92). When the second reference voltage (92) exceeds the output voltage (42), the second comparator (88) changes state. The pulses are width modulated to first or second width limits in response to changes of output states of the first and second comparators.

Abstract: Disclosed is a method for generating patterns to be used in a spatial light modulator having a plurality of pixels. The method includes generating an optical pattern to be placed upon the pixels of the spatial light modulator, applying the optical pattern to the pixels of the spatial light modulator, measuring the optical performance of the plurality of pixels having the optical pattern applied to it, comparing the measured optical performance to a target optical performance, and adjusting the optical pattern applied to the plurality of pixels to form another optical pattern that more closely achieves the target optical performance.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A mass data storage device (10) and methods for making and using it are disclosed. The mass data storage device (10) has a read/write head (18) carried in proximity to one end of a selectively positionable arm (42), and an actuation device (20) in proximity to another end of the arm for moving the arm in response to an input signal (31). The mass data storage device (10) has a sensor, such as an accelerometer (38), or the like, carried on the arm (42) for generating a motion signal for use in position control of the arm (42). The sensor (38) is located on the arm (42) at a location at which the motion signal (39) and the actuator input signal (31) have a minimum phase difference. The signal (39) from the sensor (38) may be fed back to control the actuation device (20), and may include a filter (60) that shapes the motion signal to equalize any resonances in the arm or rejects torque effects of the arm (42).

Abstract: A means to minimize physical distortion and modifications in the electrical properties of ferroelectric films incorporated into semiconductor devices is proposed. By introducing crystallographic texture into these ferroelectric films, the piezoelectric coefficient of the material can be minimized, reducing the interaction between a voltage across and mechanical stress on the film. In addition to having low piezoelectric coefficients, rhombohedral lead zirconate titanate films oriented along (111) exhibit low coercive fields and high remnant polarization, increasing their usefulness in layered semiconductor devices.

Abstract: A dynamic random access memory (DRAM) cell and associated array are disclosed. In a first embodiment, the DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) is formed within a silicon mesa (310), and includes a source region (316), drain region (318) and channel region (320). The channel region (320) is formed below a furrow (322) that is inset with respect to the top surface of the silicon mesa (310). The channel region (320) has a smaller thickness than that of the source region (316) and drain region (318). A top gate (314) is disposed over the channel region (320). Due to the reduced thickness channel region (320), greater control of the operation of the pass transistor (302) is provided, including an off state with reduced source-to-drain leakage. The greater thickness of the source region (316) and drain region (318) (relative to the channel region (320)) provides greater immunity to the adverse effects of contact spiking.

Abstract: A method and circuit (16) for driving a polyphase dc motor (14) of the type used in a mass data storage device (10) includes a commutator (55) for commutating drive voltages among windings (44-46) of the dc motor (14). In each commutation cycle, drive voltages are applied to two windings and a current summed from currents induced by the drive voltages is sunk from a third winding. A circuit (76) is provided for pulse width modulating the drive voltages during successive phase commutation cycles in respective pulse width modulated (PWM) cycles, and a circuit (66) is provided for measuring an amount of energy delivered to the motor from a beginning of each PWM cycle. A circuit (78-80, 70-72) terminates the drive voltages in a PWM cycle when the circuit (66) for measuring measures a predetermined amount of energy that has been delivered to the motor during the PWM cycle.

Abstract: The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.

Abstract: A monolithic, low power, digital-to-analog converter (DAC) circuit which uses an efficient transistor element to perform both switching and resistive current division functions simultaneously. This allows a R-2R type ladder network to be built using only conventional MOS transistors which can both switch and accurately divide current among the branches of the ladder network, without the need for separate resistors. The lower parts count and requirement for MOS transistors only, without the need for separate resistors, makes this circuit very compatible with low cost monolithic implementation. The DAC of this patent is useful in an application requiring the multiplication of two analog signals, where one of the signals is presented as a digital word. In this application, a Gilbert multiplier circuit is used to multiply the two signals, Vdig and Vsig, where Vdig represents the binary-weighted discrete levels from the DAC and Vsig is a continuous analog signal.

Abstract: Method and system of interconnecting conductive elements includes forming a lower conductive element (14) having a lower contact section (22) with a width (24) not more than substantially that of an adjacent section (26) of the lower conductive element (14). A first insulation layer (18) may be formed outwardly of the lower conductive element (14). An upper conductive element (16) may be formed outwardly of the first insulation layer (18). The upper conductive element (16) may have a upper contact section (28) with a width (30) not more than substantially that of an adjacent section (32) of the upper conductive element (16). A second insulation layer (20) may be formed outwardly of the first insulation layer (18) and the upper conductive element (16). A contact hold (40) may be formed in the first and second insulation layers (18, 20) exposing a lower contact area (42) of the lower contact section (22) and an upper contact area (44) of the upper contact section (28).

Abstract: Disclosed is a process for preparing a semiconductor device comprising the steps of adhering a back surface of a wafer, a front surface of which has been formed a circuit, onto the radiation curable adhesive layer, dicing the wafer into chips, rinsing, drying, irradiating the adhesive layer with radiation to cure said adhesive layer, expanding the adhesive sheet if necessary to make the chips apart from each other, then picking up the chips, mounting the picked chips on a lead frame, bonding, and molding to give such a structure that the back surfaces of the chips are partially or wholly in contact with a package molding resin, wherein the radiation curable adhesive layer comprises 100 parts by weight of an acrylic adhesive composed of a copolymer of an acrylic ester and an OH group-containing polymerizable monomer and 50-200 parts by weight of a radiation polymerizable compound having two or more unsaturated bonds, and the radiation curable adhesive layer has an elastic modulus of not less than 1×109 d

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.

Abstract: A frequency determination circuit generating a clock signal phase-locking with an external clock signal at a coarse precision and a fine adjust circuit generating an internal synchronizing signal phase-locking with the external clock signal at a fine precision are provided. The fine adjust circuit has a function of adjusting the phase of the frequency determination circuit when phase synchronization is to be carried out exceeding the adjust range thereof. The frequency determination circuit and the fine adjust circuit receive a clock power supply voltage. A clock reproduction circuit is provided which generates an internal clock signal phase-locking with an external clock signal or a reference clock signal stably even when the operating environment changes.

Abstract: A small-sized and light-weight projector apparatus capable of projecting images of high picture quality. A color separation/synthesis section of a projector apparatus includes a glass block body composed of a plurality of glass blocks combined together in such a manner that the corresponding sides are in close contact with each other; and a plurality of dielectric multilayer films for separating corresponding component rays of white light included in incident light and for synthesizing emitted rays from a plurality of corresponding spatial modulators.

Abstract: A control circuit is provided which includes a single programmable terminal for controlling a plurality of modes, functions or parameters in a programmable circuit with a minimum of program elements connected to the single programmable terminal. The program elements may illustratively be resistors, capacitors, inductors or other circuit components. In a first mode, for example, two program elements control a signal generating function in the programmable circuit. In a second mode in this example, a voltage provided internally forces a condition at the programmable terminal to control another signal generating function. In both first and second modes, the values of the program elements, selectable by the user, also determine the particular frequencies of the respective generated signals. In a third mode, the signals generated in the first and second modes are compared to provide yet another a control function.

Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.

Abstract: A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.