Abstract: A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.

Abstract: Integrated circuit structures comprising an embedded ferroelectric memory cell and methods of forming the same are described. These structures include a transistor level, a ferroelectric device level, a first metal level, an inter-level dielectric level and a second metal level. In a first embodiment, the ferroelectric device level is disposed over an isolation layer of the transistor level and an isolation layer of the ferroelectric level has one or more vias that are laterally sized larger than corresponding contact vias extending through the transistor isolation layer and aligned therewith. In a second embodiment, the first metal level and the ferroelectric device level are integrated into the same level. In a third embodiment, the ferroelectric device level is disposed over the first metal level. In a fourth embodiment, the ferroelectric device level is disposed over the inter-level dielectric level that, in turn, is disposed over the first metal level.

Abstract: Improved methods of forming PZT thin films that are compatible with industry-standard chemical vapor deposition production techniques are described. These methods enable PZT thin films having thicknesses of 70 nm or less to be fabricated with high within-wafer uniformity, high throughput and at a relatively low deposition temperature. In one aspect, a source reagent solution comprising a mixture of a lead precursor, a titanium precursor and a zirconium precursor in a solvent medium is provided. The source reagent solution is vaporized to form a precursor vapor. The precursor vapor is introduced into a chemical vapor deposition chamber containing the substrate. In another aspect, before deposition, the substrate is preheated during a preheating period. After the preheating period, the substrate is disposed on a heated susceptor during a heating period, after which a PZT film is formed on the heated substrate.

Abstract: A method and circuit for measuring a charge distribution for readout from a memory such as a FeRAM uses on-chip compression of bit line voltage measurements. One embodiment includes a compression circuit coupled to sense amplifiers. Each sense amplifier compares a series of reference voltages to a corresponding bit line and sets a result value for the comparison. A series of result values from a sense amplifier has a transition when the bit line voltage is approximately equal to the reference voltage. The compression circuit can use the transition as a trigger to record a compressed value indicating the reference voltage at the transition.

Abstract: A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).

Abstract: Disclosed is an add-drop multiplexer that receives an optical signal having a plurality of channels. The multiplexer spatially separates the channels, and a spatial light modulator within the multiplexer, which in some embodiments is a switched blazed grating, routes the channels along first or second paths according to whether the particular channels are to be sent along as a part of an output communication signal or “dropped” into a dropped-channel optical communications signal. The add-drop multiplexer is also operable to receive optical channels to be added to an optical signal and to use a spatial light modulator to add those optical signals to that optical signal.

Abstract: A comparator-type sense amplifier compares a constant voltage that was read out of a FeRAM cell to a sequence of reference voltage levels. A multiple-comparison operation includes (a) reading out data to a bit line, (b) applying a first/next reference voltage, (c) comparing the bit line voltage to the applied reference voltage, and (d) repeating steps (b) and (c) one or more times. The multiple comparison operation can be used to characterize operation of an FeRAM cell, predict or detect an FeRAM cell that may introduce a bit error, or to read a multi-bit value from an FeRAM cell.

Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.

Abstract: The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.

Abstract: An improved method for fabricating a window frame/window piece assembly is disclosed in this application. A window frame having an opening in its inner portion is provided. According to one aspect, the window frame can be formed from a unitary piece of sheet metal. A transparent piece is attached to the inner portion of the window frame through a molding process. According to one embodiment, the window frame is placed within a mold such that the inner portion of the window frame projects into an inner cavity inside the mold. After the mold has been closed, a transparent material is injected into the inner cavity so that it bonds with the inner portion of the window frame. After the bond of between the transparent material and the window frame is set, the window frame/window piece assembly is removed from the mold. According to another embodiment, a plurality of window frames may be loaded into a single mold so that a plurality of window frame/window piece assemblies can be fabricated in a single batch.

Abstract: An integrated circuit device includes a two-dimensional array of ferroelectric memory cells in which plate lines within the array are grouped. The grouping of plate lines accommodates the use of larger plate line drivers, such as CMOS driver inverters. Each plate line group may include some but not all of the rows of memory cells and some but not all of the columns of memory cells within the array.

Abstract: The present application describes a system and method for selecting the best modulation sequence for an image (e.g., video, graphics or the like) on a frame-by-frame basis to optimize the system contrast ratio, brightness and black level based on a histogram of pixels in each frame. Embodiments described in this application include Pulse-Width Modulation (PWM) display systems such as DMD™. In an embodiment, the present invention uses the histogram of pixels in each frame of an image to select alternate color sequences for each frame of the image wherein the alternative color sequence includes reduced number of bits for color representations than the original color sequence.

Abstract: A memory which is capable of reconfiguration between a first mode in which each storage cell is capable of storing a pair of data bits and a second mode in which each storage cell is capable of storing a single data. A memory according to the present teachings includes a storage cell having a first structure and a second structure each capable of a storage state and mechanisms for reconfiguring the memory between a first mode in which the storage states of the first and second structures indicate a first and a second data bit, respectively, and a second mode in which the storage states combine to indicate a data bit.

Abstract: An amplifier (70) has a differential input stage (84,86). An output transistor (102) is connected to receive a single ended output developed by transistor 86. First (74) and second (76) current sources are connected to establish respective first and second currents in the input differential transistors (84,86) according to a predetermined ratio. First and second voltages are subtracted from the differential inputs (VM,VP) in respective differential amplifiers (88,90), and the output is derived from the output transistor having a magnitude proportional to an inverse of a product of a square of the reference resistance, a carrier mobility, and an oxide capacitance.

Abstract: A method and apparatus for measuring the transient behavior characteristics of individual micromirrors in a DMD micromirror array. The method and system use sampling techniques to measure an amount of light reflected by an individual micromirror as the entire micromirror array is stimulated with a pattern of alternating driving signals. Sampling is achieved by illuminating the DMD micromirror array with a high-speed illumination source that provides stroboscopic light flashes of very short time length. By synchronizing the light flashes with the mirror driving signal and measuring the amount of light reflected by the individual micromirrors at different points in time, the transient behavior characteristics of individual micromirrors in a DMD micromirror array can be measured with a high level of accuracy.

Abstract: A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a part of the wafer.

Abstract: An improved window frame and window piece for a micromirror assembly is disclosed herein. The window frame includes a stress-relieving contour positioned in the middle of the frame that can absorb the mechanical stresses applied to the window frame from the ceramic base and from the window piece. The window frame may be comprised of a single piece of sheet metal that has been stamped to include a stress-relieving contour. The stress-relieving contour may be comprised of a variety of shapes, including a “U” shape, an inverted “U” shape, a curved step shape, or other combinations thereof.

Abstract: The present invention is related to a method for reducing the metal contamination on a surface of a semiconductor substrate wherein said substrate is submitted to a wet cleaning or rinsing process in a solution capable of oxidising said surface and containing a substance strongly dissociating in said solution whereby creating an amount of ions of at least one species in said solution, at least one of the ion species being such that the ions of the species are binding to the oxidised surface in such a way that said amount of ions is substantially reducing the amount of metal ions bound to the oxidised surface. Wet treatments such as rinsing, cleaning, in wet benches, batches and single wafer wet-cleaning equipment and single or double-side cleaning or etching applications can use the method of the present invention.

Abstract: A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A comparator-type sense amplifier and a reference voltage generator measure a bit line charge or voltage using one readout of charge from an FeRAM cell and comparisons of the resulting bit line voltage to a series of reference voltages. A series of result signals from the sense amplifier indicates when the bit line voltage is approximately equal to the reference voltage. The results signals can be output for analysis and/or used internally for defect detection or setting of operating parameters such as a reference used during read operations.

Abstract: Disclosed is a mounting system and method in which symmetrical springs are used about a collar in a gimbal system to capture an assembly of a ball and an optical or other type of component. Once captured within the mounting system, the ball/component assembly can pivot until an optimal alignment is reached. Once the optimal alignment is reached, the ball/component assembly is fixed using laser welding.