Abstract: A cordless telephone is described comprising a fixed part which includes a reception section for receiving exact reception channel frequencies lying in a predetermined frequency range at equal intervals apart and a transmission section for transmitting exact transmission channel frequencies lying at a predetermined duplex interval from the reception channel frequencies. The cordless telephone further comprises a mobile part which includes a reception section for receiving frequencies lying in the range of the transmission channel frequencies of the fixed part and a transmission part for transmitting frequencies lying in the range of the reception channel frequencies of the fixed part. The mobile part includes a frequency control loop which using the transmission channel frequency transmitted by the fixed part as reference frequency holds its reception section fixedly tuned to the received transmission channel frequency.

Abstract: An integrated circuit oscillator which includes a capacitor, a reference current source coupled to the capacitor used to charge the latter, and a trigger circuit coupled to the capacitor having an upper input threshold for changing from a first state to a second state and a lower input threshold for changing from the second to the first state. A discharge circuit is coupled to the trigger circuit and is operative to discharge the capacitor in response to the trigger circuit changing states and to cease the discharging on changing back to its original state.

Abstract: Column decoding is performed using multiply decoded subsets of column address bits bussed across the array to multiple first stage and second stage column multiplexers. That is, for example, in an 8k by 9 memory wherein each subarray contains 16 selectable columns at each bit position, two of the address bits would be fully decoded to provide four buss lines across the chip. Each column has a primary sense amplifier, controlled by one of these four decoded lines. The outputs of each set of four primary sense amplifiers are multiplexed into a secondary sense amplifier, (preferably on a local three-scale buss) and the output of each secondary sense amplifier is selected or deselected by four buss lines which are the decoded signals corresponding to the other two address bits which select one of 16 columns. Preferably multiplexing of the output of the secondary sense amplifiers is accomplished by a three-state buffer, so that the output of these buffers can be accomplished as a wired-or function.

Abstract: A video display system employs a memory arrangement for the video data which is sequentially accessed for serial read-out of the bit-mapped video information at a high clock rate, and also randomly accessed in parallel by a microcomputer for generating and updating the information to be displayed. Parallel access to the memory by the microcomputer can occur while the serial video data is being clocked out, so microcomputer I/O and video output conflict only a very minimum amount. Dynamic MOS RAMs with a serial register added provide this dual port memory.

Abstract: An electrically programmable semiconductor memory device of a type having an array of programmable semiconductor floating gate transistors sets of which are coupled between associated respective source and drain lines, an array programming control transistor and a ground select transistor coupled to each of the drain and source lines. Each selected floating gate transistor in a programming mode is in series with control and ground select transistors between a high voltage Vpp and ground potential. A resistive element in series with a first conducting circuit element establishes a reference current which generates a voltage V.sub.1 at the junction of the resistive element and the circuit element. In a second current leg a second conducting circuit element, a module floating gate transistor biased into a conducting state and a module control transistor are all connected between Vpp and ground such that a voltage V.sub.

Abstract: A method of reducing Rayleigh waves (ground roll) in land seismic exploration employs a unique combination of amplitude output from and spacing of the vibrator sources making up a land seismic exploration system. The velocity of the Rayleigh wave for the prospect to be explored is determined. At least one receiver is used and is spaced from the vibrator sources a distance sufficient to establish the receiver as being in the far-field. The output of each of the vibrator sources is locked in phase and frequency and known separations between the vibrator sources are maintained. The frequency is varied and the individual output amplitude of each vibrator source is varied at each frequency so that the resultant Rayleigh waves traverse the known separations resulting in out-of-phase Rayleigh waves between the sources.

Abstract: An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V.sub.BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V.sub.T above V.sub.BIAS. Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V.sub.T about V.sub.BIAS. The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.

Abstract: A three terminal tunneling device analogous to a field effect transistor is disclosed. Preferred embodiments include a planar quantum well (52) with a gate insulator (56) and gate (58) on one surface and with a tunneling barrier (54) and source (62) and drain (60) on the other surface. The conduction current comprises electrons tunneling from the source (62) into the well (52) and then out into the drain (60). The gate (58) bias shifts the well subband levels up and down to establish and disrupt resonance for the tunneling from the source (62) into the well (52). Other preferred embodiments include interdigitated source and drain, multiple gates, multiple wells, and floating gates.

Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.

Abstract: A multiple oscillator switching circuit for a digital processing system that includes a central processing unit having a first internal timing cycle and connected to a plurality of peripheral devices, each peripheral device having an independent internal timing cycle. The central processing unit is further connected to an oscillator switching circuit. The oscillator switching circuit includes several oscillators. Each oscillator has an output consisting of an independent internal frequency. A selected number of these oscillators have independent internal frequencies that correspond to the internal timing of the peripheral devices. These oscillator switching circuits are further connected to the central processing unit and to the output of each of the oscillators for providing a single oscillator output to the central processing unit in response to an output from the central processing unit.

Abstract: A contact and interconnect for an MOS VLSI semiconductor device employs a contact hole in an insulator coating; the contact hole has vertical instead of sloped sidewalls. A first metallization is applied by CVD so that the sidewalls will be coated to a uniform thickness, then this first metal is anisotropically etched to leave metal sidewalls. A second metallization is applied by sputtering or evaporation, which provides a more dense and electromigration-resistant coating. A refractory metal layer may be interposed between the metallization and the silicon substrate, and also between the metal interconnect and the insulator, since the insulator usually contains phosphorus.

Abstract: In a video computer system and the like having a bit-mapped RAM component including a shift register, an improved method is provided for rapidly clearing the RAM in order to prepare the system to receive new input data. More particularly, a preselected number of predetermined data bits corresponding to the number of columns in the RAM is serially shifted into the register. Thereafter, the contents of the shift register are progressively shifted into each of the rows in the RAM until all rows are filled.

Abstract: A structure for a focal plane array substrate is disclosed that includes a focal plane array positioned above a semiconductor substrate containing a signal processor. The signal processor is connected to the image detection elements of the focal plane array by connections through the focal plane array chip itself. A method for interconnecting an image array to a signal processor located beneath the image array is also disclosed. This method includes forming holes in the imager array and forming buses connecting the imager array elements to conductors located in the holes that extend to bonding pads connected to the signal processor located below.

Abstract: A bi-planar pontoon paravane is towed by a marine vessel and controls the depth and position of a towed seismic source array. The bi-planar pontoon paravane is made up of a buoyant bridge with right and left wings attached to the long sides of the bridge, the wings projecting into the water and, in concert, providing a side force. The paravane is towed by a tow line connected to an adjustable bridle which in turn is connected to the paravane. Remote adjustment of the bridle is provided by an hydraulic valve on the vessel controlling an hydraulic motor and gear arrangement on the paravane to adjust the bridle. Adjustment of the bridle adjusts the angle of attack of the paravane. The paravane provides a housing formed below the bridge and between the two wings for housing the seismic source array. A boom on the vessel is attached to the seismic source array, through the bridge, when the assembly is to be placed in or removed from the water.

Abstract: A method of plasma etching blind vias in printed wiring board dielectric which comprises the steps of providing a printed wiring board of organic material having a buried electrically conductive pattern in the organic material and an electrically conductive layer on the surface of the board, removing predetermined portions of the electrically conductive layer to expose the organic material thereunder and define at least one via location thereat, providing a plasma etching chamber having one or more pairs of spaced parallel electrodes, positioning the board between the said electrodes, electrically connecting the board to one of said electrodes and having the surface facing and parellel to the electrodes, filling the chamber with a mixture of an oxidizing gas and a fluorocarbon gas, etching the organic material from the exposed organic material at the surface to the buried pattern to expose the buried pattern by applying an RF signal across the electrodes, and forming an electrically conductive layer of the ex

Abstract: A fuse selectable decoder for a redundant row of memory elements in an array includes a redundant decode select circuit (38) for receiving predecoder inputs from predecode lines (28), (30), (32) and (34). The predecode lines are output from predecoders (20), (24) and (26) which decode an eight bit address word. The redundant decode select circuit (38) is programmed by fuse select circuit (40) that selects the address of a defective one of the rows of memory elements in an array (10). The redundant decode select circuit (38) selects one line out of each of the predecode lines (28), (30), (32) and (34) for input to an AND gate (112) for selecting the redundant row (12).

Abstract: A vacuum processing system for processing semiconductor wafers includes a particle shield (16) disposed above the wafer (10) to block moving particles in a vacuum chamber which would otherwise contact the wafer (10). The particle shield (16) is attached to arm (18), allowing the particle shield (16) to be moved away from the wafer or photomask during processing.

Abstract: An ion source of a type used on ion implanters which includes a crucible having a hollow interior and a hole for providing fluid communication between the interior of and exterior to the crucible. A heater assembly is used for adjustably heating the crucible. The crucible hole is if fluid communication with a passageway down the crucible and with a vapor nozzle aperture. An arc chamber has an inlet positioned at the output of the vapor nozzle aperture. The material to be vaporized does not bond to the crucible interior when solidified from a liquid state.

Abstract: A high reliability low cost connector has flat retainers blanked from an electrically conductive sheel metal and inserted into opening in an electrically insulating body. Each retainer has a post at one end extending from an opening at one side of the body and has a pair of integral wings spaced from each other in a plane at its opposite end disposed in the opening at the opposite side of the body. Spring clips are blanked and formed from an electrically conductive sheet metal spring material and are inserted into the body openings so loop portions of the clips fit between the pairs of retainer wings in each opening and are biased into resilient electrical engagement with the retainer wings. Each clip preferably has two pairs of juxtaposed spring leaves integral with the loop spaced at 90.degree. relative to each other around a common axis to grip a terminal inserted between the spring leaves. The loops are also formed with interruptions in each loop in a common location between two adjacent spring leads.

Abstract: Varactors are incorporated in a monolithic microwave integrated circuit (MMIC) to provide voltage-programmable impedance matching at inputs and/or outputs. This permits the impedance variations normally caused by manufacturing variations in (e.g.) doping or epitaxial thickness to be easily compensated by adjusting the varactor bias, after all major manufacturing steps are completed.Integrated varactors are also used to provide temperature compensation in an MMIC. A temperature-sensitive voltage is generated off-chip and supplied to each on-chip varactor. Each varactor may include a respective voltage-shifting network, so that different varactors implement different capacitance (temperature) functions, to optimally compensate different portions of the MMIC.