Abstract: A circuit for sensing a voltage present on an input line higher than a supply voltage V.sub.DD which includes an isolation switch coupled between the input line and an output line, a threshold adjustment diode coupled in series with the isolation switch also between the input and output lines for establishing a voltage above V.sub.DD at which the isolation switch turns on and a constant current source coupled from an output of the sensing circuit and ground.

Abstract: Structures (30) with IMPATT type diodes (34) located periodically along a transmission line (38-32) to simulate a distributed diode are disclosed. Preferred embodiments include incorporation of the periodic diode structures as the gain element of microwave amplifiers and oscillators. Preferred embodiments also place capacitors between the diodes to fix nodes in the electric field and increase the effective structure size.

Abstract: A light modulator and a high speed spatial light modulator (230) with each pixel (231) made of stacked quarter wavelength layers (232, 234) of heterogeneous material. Each layer (232, 234) is composed of periodic quantum well structures whose optical constants can be strongly perturbed by bias on control electrodes (240, 242). The control electrodes (240, 242) act to either remove light absorbing electrons from the layer or to inject them into each layer. The effect is to produce either a highly relecting mirror or a highly absorbing structure. The spatial light modulator (230) is compatible with semiconductor processing technology. Also, a modulator invoking the Burstein effect in the form of a stack of p-n diodes is disclosed.

Abstract: A vision system provides an apparatus and method for obtaining an image of a manufacturing apparatus that is electrically controllable. A gray scale image of the manufacturing apparatus is obtained and is used to generate control commands that control the manufacturing apparatus.

Abstract: A voice control system for controlling execution of a computer program includes a microphone (10) operative to receive voice commands having the output thereof connected to a clipping circuit (12) which amplifies and clips the microphone output to generate a zero-crossing signal. The output of circuit (12) is connected to a microprocessor (14) which on detecting speech input interrupts program execution in a CPU (15) and "freezes" display device (16) on which the game is displayed. Microprocessor (14) then processes the input signal to recognize the voice command by determining the relative frequency content of discrete portions of the command. Once it has recognized the command, microprocessor (14) prompts the CPU (15) to execute the command and resume execution of the game program at the point of interrupt. By suspending the progress of the game during the speech input and recognition interval, the voice control system minimizes the time-constraint problems associated with voice input.

Abstract: A two transistor Dynamic Random Access Memory Cell and Array. Use of two pass transistors in series for the cell provides numerous additional capabilities for the DRAM array, and, in the preferred embodiment, provides bitline segment multiplexing, so that the sense amplifier pitch can be increased while the bitline capacitance as seen by the sense amplifier and by the memory cell is reduced. To accomplish this, the parasitic capacitance of the node between the two series pass transistors is kept to a minimum.

Abstract: The disclosure relates to a bipolar transistor having reduced base-collector capacitance and a method of making the transistor by forming a sidewall base contact with polycrystalline silicon-on-insulator. The structure is achieved by using differential oxidation to grow thicker oxide over heavily doped N+ regions in a sacrificial polycrystalline silicon layer with the sidewall base region being protected from doping by a sidewall oxide and limited anneal of the N+ dopant. Both NPN and PNP bipolar transistors with minimum collector-base capacitance can be fabricated using this technique.

Abstract: The specification discloses an input transistor (14) which is variable between high and low impedance states in response to input voltage transitions at terminal 10. An output transistor (16) is coupled to the input transistor (14) and is responsive to an input transition at terminal 10 for changing impedance states. Circuitry including a speed up transistor (44) is coupled between the input transistor (14) and output transistor (16) for applying added current to the output transistor (16) to speed the change of impedance state. The circuitry applies added current to output transistor (16) until the output voltage at terminal (18) falls below twice the base-emitter voltage of the output transistor (16).

Abstract: A plasma dry etch process for etching deep trenches in single crystal silicon material with controlled wall profile, for trench capacitors or trench isolation structures. HCl is used as an etchant under RIE conditions with a SiO2 hard mask. The SiO2 hard mask is forward sputtered during the course of the Si etch so as to slowly deposit SiOx (x<2) on the sidewalls of the silicon trench. Since the sidewall deposit shadows etching at the bottom of the trench near the sidewall, the effect of this gradual buildup is to produce a positively sloped trench sidewall without "grooving" the bottom of the trench, and without linewidth loss. This process avoids the prior art problems of mask undercut, which generates voids during subsequent refill processing, and grooving at the bottom of the trench, which is exceedingly deleterious to thin capacitor dielectric integrity.

Abstract: A computer system reviews and modifies horizons tentatively defined by a network of pairs of turnings. The curvature for each of the paths of turnings of the network in both the X and Y directions is assessed. If the curvature exceeds a predetermined value in any of the paths, that path is terminated at the point of excessive curvature. Also, each pair of turnings is tested to determine whether it is in a closed loop made up of four turnings which in turn make up four pairs of turnings to determine that there is three-dimensional continuity. The horizons are thereby modified if modification is required.

Abstract: A thermostat comprises a bimetal switch element reacting upon changes in temperatures which on one of its ends is fastened to a frame and on its other end is provided with an electric contact adapted to engage a fixed contact provided on the frame. The frame comprises two mutually parallel sheet-like metallic contact carriers forming a base unit, through which two parallel pins are extending for connection of both contact carriers and on which pins the contact carrierrs, with a tight fit, are slidable to and fro relative to one another while being held in permanent mutually parallel relation during the sliding. The parallel pins in the thermostat are formed of a ceramic material of positive temperature coefficient of resistivity which serve to electrically space the two metallic contact carriers while also serving as a self-regulating external heating means for the thermostat.

Abstract: A unital casing structure of a portable electronic appliance such as a handheld or desktop calculator, comprising at least two panel sections having a straight boundary line therebetween and integrally coupled together across the boundary line whereby the panel sections are foldable with respect to each other about an axis extending along the boundary line between the panel sections so that the two panel sections are coupled together in a face-to-face relationship. The casing structure may further comprise an intermediate panel section bridging the two panel sections, the intermediate panel section being angularly movable with respect to the two panel sections about two axes parallel with and spaced apart across the boundary line between the panel section and being foldable with respect to each of the two panel sections about each of the two axes.

Abstract: A modularized scanned logic test system includes modularized logic circuits (26) having control/observation locations therein. Each of the control/observation locations has a shift register latch (SRL) disposed thereat. A common scan data in line (28) provides data to a serial input to each of the modules (26). The serial output of each of the modules (26) is interfaced with a scan data out line (30). An address on a bus (16) is provided to a decoder (52) to select one of the modules (26). An isolation gate (48) allows for input of data to only the select one of the modules (26) and an isolation gate (50) allows output of data only from the select one of the modules (26) to the scan data out line (30).

Abstract: A motor protector having a thermostat metal element thermally coupled to an electrical motor in a refrigerator compressor motor system has a heater responsive to motor current thermally coupled to the thermostat metal element and has an improved component arrangement to provide locked rotor and ultimate trip protection for the motor without requiring calibration of the operating temperature for the protector after assembly or after incorporation in the motor system.

Abstract: Disclosed is a method for determining whether or not two signatures were written by the same individual. An X-Y data tablet indicates the location of the writing instrument at a predetermined clock pulse rate as the signature is written. A number string is generated which indicates the relationship between sequentially determined locations of the writing instrument as it moves to different locations on the X-Y data tablet. The quantity of numbers within the number string is an indication of the distance between sequentially determined locations and the value of the numbers within the number string is an indication of the direction of movement between sequentially determined locations. Series of number strings form a waveform representative of the signature as written by the individual. The waveform of the sample signature is compared with the waveform of a reference signature and an output is provided indicating whether or not the sample signature and the reference signature were made by the same individual.

Abstract: A clock delay circuit of the type used in semiconductor dynamic read/write memory device employs pull-up and pull-down output transistors connected in series between a voltage supply and ground. Excess current in this series path is minimized by a circuit holding the gate of the output pull-up transistor to a low voltage until the gate of the pull-down transistor goes low. Then, the gate of the pull-up transistor is booted above the supply voltage. Also, tendency for the output voltage to rise above ground during the delay period is avoided.

Abstract: A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a quasi-folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects one of the two segments to be connected to one of the two bit lines. Instead of being interleaved one-for-one, the word lines for cells to be connected to the two bit lines are in groups one group for each segment line; the groups are interleaved. The combined segment line and bit line capacitance has a more favorable ratio to the storage capacitance, compared to the one-for-one interleaved layout.

Abstract: A chemical beam epitaxy system including a cylindrical vacuum chamber (32) with wafer heaters (42) affixed about the cylindrical wall, a rotatable wafer holder ring (40) with mounted wafer holders (38) adjacent the wafer heaters (42), and a central rotatble set of gas cells (44) for directing chemical beams (50, 54) across wafers (52) in the wafer holders (38).

Abstract: A semiconductor integrated circuit has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi.sub.2 or WSi.sub.2. Adhesion of the metal silicide to the polysilicon is enhanced by forming a thin silicon oxide coating on the polysilicon before sputtering the metal silicide. The resulting structure has low resistance but retains the advantages of polysilicon on silicon.

Abstract: A system for processing a plurality of Equations includes a single full adder (44) which has the A input thereof multiplexed by multiplexer (62) and the B input thereof multiplexed by a multiplexer (94) and a multiplexer (66). The multiplexer (94) is operable to select a multiplicand for multiplication operations from a delay stack (54) for multiplication operations. The multiplication operation is performed by adding together partial products recording to Booth's modified algorithm. The partial products are generated by recode logic circuit (90) and (98). The recode logic circuits (90) and (98) are controlled by the multiplexed output from the multiplexer (80) which selects bits of a given multiplier stored in a K-stack (72). The multiplexer (62) in conjunction with the recode logic circuits (90) and (98) control reconfiguration of the adder (44) as a multiplication circuit.