Abstract: A keyboard is assembled by providing first and second electrically conductive strips of layers and first and second electrically insulative strips of layers, forming the layers into a desired configuration and laminating them together with the respective insulative layers intemediate and on top of the conductive layers. Switching areas are delineated on at least one of the conductive layers and are joined to each other and are provided with output leads by conductive paths configured from the conductive layer. The interposed insulative layer is formed with a plurality of apertures located so that an aperture can be aligned with each switching area. After the layers are laminated together they are blanked out from the strips and holes are punched out through the four layers to sever selected conductive paths and form a preselected circuit pattern.

Abstract: A cross point EPROM array has trenches to provide improved isolation between adjacent buried N+ bitlines at locations where the adjacent buried N+ bitlines are not separated by a FAMOS transistor. This results in improved leakage current, improved punchthrough voltage characteristics, and in improved programmability for the cell.

Abstract: Video display of stored text is accompanied by associated speech from a speech synthesizer using coded sounds and intonation. A central processor controls selection of text and speech. Speech is selectable in one of a plurality of prestored languages coded in frequency and duration data.

Abstract: A multi-level logic circuit includes a first plurality of logic circuits that are connected in a cascade arrangement. A second plurality of dummy logic circuits also connected in casacade arrangement are used to generate logic pulses for evaluating the first plurality of logic circuits. A clock source provides a precharged signal to the first plurality of logic circuits and the second plurality of dummy logic circuits and an evaluation circuit is used to combine the clock signal with an output signal from the dummy logic signal to obtain an evaluation signal for evaluating the logic states of the first plurality of logic circuits.

Abstract: A rack for use in mounting a plurality of input/output modules in a programmable controller or process control computer system or the like has a plurality of first connectors mounted on a circuit board for making detachable electrical connection to the respective modules and has second connector means for connecting the circuit board to the controller system. A rack member molded of a stiffly resilient insulating material has a bottom with apertures therein mounted over the circuit board to permit access to the first connectors and has a pair of juxtaposed integral side walls upstanding from the bottom of the rack to engage respective opposite latteral edges of the modules to guide the modules into respective first connectors in compact side-by-side relation to each other within the rack member.

Abstract: An injection mold is described for producing the housings of integrated circuits. The injection mold icludes a first mold half (30) in which are disposed a number of mold recesses (46) corresponding to the number of housings to be made simultaneously, having a depth corresponding to a portion of the height of the housings, and supply passages (48, 50, 52, 54, 56, 58) leading to the mold recesses (46). In a second mold half (32) which is adapted to be brought in the closure direction into engagement with the first mold half (30) a number of mold recesses (76) equal to the number in the first mold half (30) are disposed in corresponding arrangement, the depth thereof being equal to the remaining portion of the height of the housings to be made. The mold recesses (46) in one of the mold halves (32) are disposed groupwise in mold portions (64) which are held in the one mold half (32) displaceably in the closure and opening direction.

Abstract: A smart mine includes a pair of He.sup.3 magnetic sensors exteriorly connected to a head compartment of a mine housing. A torpedo compartment for housing a torpedo completes the mine housing. The head compartment contains the sensor support electronics which includes a phase locked loop means having a pair of digital phase locked loops connected between the sensors and a difference circuit whereby a difference signal representative of the difference between the pair of He.sup.3 magnetic sensors is produced for processing in a signal processor for determining the presence of large ferromagnetic bodies and producing a torpedo firing signal.

Abstract: A single chip multiprocessor interface device for interfacing between two processors by connection to their bus systems, the device having a random access memory selectively accessible by the processors under the control of an arbitration latch. The arbitration latch has a bistable device the state of which determines which processor has access to the memory. The outputs of the bistable device have threshold devices which have threshold levels higher than the signal outputs of the bistable device when it is in a metastable state, so that there is no possibility that both processors could have access to the memory at the same time. Data and address registers for the two processors are selectively connectible to the random access memory through multiplexers controlled by the arbitration latch.

Abstract: A transparent shift register latch (170) includes a normal operating gate (182) and a test gate (184) for selectively connecting data to a node (180). The node (180) is input to an isolation gate (186) through an inverter (188) for connection to an output node (190). A peripheral port (172) is interfaced with the output node (190) through an isolation gate (192). The gates (186) and (192) are operable in a test mode to interface data stored on the node (180) with the output of the latch (170) and inhibit input of data from the port (172). In the normal operating mode, the isolation gate (192) is closed and the isolation gate (186) is opened. The transparent shift register latch (170) allows testing of interface lines between adjacent logic modules.

Abstract: The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.

Abstract: A broadband two arm planar/conical/helix antenna is disclosed. The antenna radiation element includes a two arm planar spiral antenna section, a two arm conical spiral section connected to the planar spiral section and a four arm helix section connected to the conical spiral section for termination. The antenna element is formed on a fiberglas substrate which contains a molded internal load absorber. A tapered magnetic external load absorber covers the antenna radiation element. The supporting fiberglas substrate is fixed to a balun housing. The balun housing has a centrally disposed, upwardly extending tubular means for passing a feed line to the planar spiral section.

Abstract: A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.

Abstract: An ultrasonic generator for providing power to a bonding apparatus having a bonding horn which is brought into contact with respective conductive pads and which carries a wire to be dispensed for interconnection therebetween includes a circuit for applying a voltage at an ultrasonic frequency to the bonding horn to produce a bonding current in the horn, and a monitor for monitoring the bonding current applied to the bonding horn. A circuit is provided for maintaining a zero phase difference between the applied voltage and the monitored current. In addition, a circuit is provided for continuously monitoring and controlling the current which is delivered to the bonding horn to produce a current waveform of a predetermined controllable pattern.

Abstract: A thermostat equipped with a bimetallic element sensitive to a given temperature comprises a monolithic base open at one end in which two terminals connectable to an electric circuit are inserted and precisely located, each having one end bent at a right angle and each carrying a stationary contact, an element carrying movable contacts for connecting the stationary contacts with one another, a spring housed in a seat on said base biasing the movable contact element to engage the stationary contacts, a sliding element for moving and guiding said movable contact-carrying element, a bimetallic element suitably spaced from the said sliding element for initiating movement of the sliding element in response to temperature change, and a lid which fastens the said bimetallic element to the said base with said spacing from the sliding element.

Abstract: A tunable multiline/multiband laser includes a partial reflecting mirror, a gain control, a diffraction grating means, and a reflective mirror means. The reflective mirror means includes in a first embodiment a fabricated mirror which allows for any number of predetermined lines and combinations, which a second embodiment replaces the fabricated mirror with a material that is capable of changing its reflectivity upon changing its thermodynamic phase state. The diffraction grating means includes a grating and a lens to spatially separate initially parallel rays of different wavelengths originating from the gain cell and project the spectrum onto the surface of the mirror means. The mirror means includes a mirror constructed to normalize the round trip gain to each frequency component. The normalization is accomplished by proper choice of reflectivities at the focal point of each wavelength upon the mirror.

Abstract: A method and apparatus for managing a block oriented memory of the type in which each memory block has an associated reference count representing the number of pointers to it from other memory blocks and itself. Efficient and cost-effective implementation of reference counting alleviates the need for frequent garbage collection, which is an expensive operation. The apparatus includes a hash table into which the virtual addresses of blocks of memory which equal zero are maintained. When the reference count of a block increases from zero, its virtual address is removed from the table. When the reference count of a block decreases to zero, its virtual address is inserted into the table. When the table is full, a reconciliation operation is performed to identify those addresses which are contained in a set of binding registers associated with the CPU, and any address not contained in the binding registers are evacuated into a garbage buffer for subsequent garbage collection operations.

Abstract: Energy normalization in speech synthesis systems is achieved by a look-ahead adaptive normalization procedure, wherein energy is adaptively tracked, and the adaptive energy-tracking value is used to normalize a much earlier frame's energy value.

Abstract: A micropackage for providing high density, three dimensional packaging of integrated circuit chips. A chipmount (10) includes a plurality of channels (36) on the bottom surface thereof for holding a corresponding plurality of integrated circuit chips (16). A shallow cavity (34) is formed on the top surface of the chipmount (10) for holding another integrated circuit (14). Metallization interconnections (22) are formed on the top and bottom surfaces of the chipmount (10) and are terminated by solder pads (24, 39). Conductive conduits (26) are formed through the chipmount (10) for providing electrical continuity between an integrated circuit chip (14) mounted on the top side, to other integrated circuit chips (16) mounted on the bottom side of the chipmount. Other conductive conduits (30, 32) and a bridging member (28) insulates intersecting conductive paths (48, 50). The micropackage is fabricated with standard silicon technology.

Abstract: The present invention provides a conversion between a speech mode in which each word is clearly enunciated as if spoken in isolation and in which a phrase is spoken as a whole taking into account the influence of adjacent words. In the phrase mode, word ending final phonological linguistic units are replaced with their corresponding internal versions, and short strong vowels are substituted for the corresponding long strong vowels except at the word ends. In the word mode, a word final pronunciation is given when a corresponding internal phonological linguistic unit occurs at a word end, and short strong vowels are replaced by the corresponding long strong vowel when the short strong vowel occurs at the end of a word or prior to a set of voiced consonants. In either mode, a substitution may be made for the pronunciation of frequently used words. This invention is most useful in speaking electronic learning aids which permit word or phrase speech synthesis from the same data.

Abstract: This voice messaging system provides an LPC analyzer in combination with a pitch extractor wherein LPC parameters and a residual signal organized in a sequence of speech data frames are provided by the LPC analyzer as an output representative of an analog speech signal. The pitch extractor is operably associated with the LPC analyzer and produces a plurality of pitch candidates for each of the speech data frames in the sequence thereof. Dynamic programming is performed on the plurality of pitch candidates for each speech data frame and also with respect to a voiced/unvoiced decision of the speech data for each frame by tracking both pitch and voicing from frame to frame to provide an optimal pitch value and also an optimal voicing decision.