Abstract: An EEPROM cell is described which includes a trench formed in the field oxide adjacent to the EEPROM cell. Both the control gate and the floating gate of the cell are formed over this trench. By forming both gates above the trench, the capacitive coupling between the gates is increased. Thus a EEPROM cell constructed in accordance with the teachings of this invention may be constructed using a smaller surface area of the integrated circuit or may utilize a smaller programming voltage to charge and discharge the floating gate.

Abstract: Speaker-independent word recognition is performed, based on a small acoustically distinct vocabulary, with minimal hardware requirements. After a simple preconditioning filter, the zero crossing intervals of the input speech are measured and sorted by duration, to provide a rough measure of the frequency distribution within each input frame. The distribution of zero crossing intervals is transformed into a binary feature vector, which is compared with each reference template using a modified Hamming distance measure. A dynamic time warping algorithm is used to permit recognition of various speaker rates, and to economize on the reference template storage requirements. A mask vector with each reference vector on a template is used to ignore insignificant (or speaker-dependent) features of the words detected.

Abstract: A semiconductor integrated circuit device includes a rigid planar member or cover affixed to and overlying at least a portion of the upper surface of a semiconductor integrated circuit bar. The upper surface of the planar member is textured to lock the member to the encapsulating medium, and has a thermal coefficient of expansion similar to that of the integrated circuit bar. According to another aspect of the invention the planar member is formed of a material having a low alpha particle emission.

Abstract: A plasma dry etch process for etching semiconductor insulating materials, such as thermally grown or CVD deposited silicon oxide, with selectivity to silicon and refractory metals and their silicides, using a fluorinated inorganic center together with a hydrogen-liberating source under glow discharge conditions. The process does not employ saturated or unsaturated fluorocarbons as etchants, thereby eliminating the polymerization problem.

Abstract: A method of fabrication for self-aligned gallium arsenide transistors using metal implant masks is disclosed. Preferred embodiments include use of a dummy gate (150) made of aluminum (144) on top of titanium tungsten (142) as an implant mask for source (52) and drain (54) formation with the titanium tungsten (142) undercut so that deposited silicon dioxide (62) will form a self-aligned mask for the gate deposition after the dummy gate (150) is removed.

Abstract: Liquid silicon is deposited on a high surface area column of silicon nitride particles, by hydrogen decomposition of trichlorosilane. This is accomplished in an environment heated to a temperature in excess of the melting point of silicon. After deposition, the liquid silicon flows by gravity to a collection point. Preferably a liquid transfer system moves the silicon directly to a crystal pulling operation. The liquid transfer to immediate pulling conserves energy and allows for continual withdrawal of melt from the reactor. The immediate pulling provides additional purification and the crystal thus pulled is preferably used as feedstock for a final crystal pulling operation.

Abstract: A Random Access Memory with error detection/correction capability includes an information array (10) for storage of a collective data word in a single row thereof and a parity array (12) for storage of corresponding parity information in a single row thereof. A single row of the information array (10) and the parity array (12) are accessed and input to an error correct circuit (54). The collective data and parity information are also input to an error syndrome/parity generator (48), the output of which is input to the error correct circuit (54) to correct bits that are in error. A latch (72) is provided for latching the corrected information therein to allow new data to be written therein. The output of the latch (72) is multiplexed into the error syndrome/parity generator (48) which is configurable as a parity generator to generate new parity information for a write operation. The new collective data and parity information in the write mode are stored in arrays (10) and (12).

Abstract: There is disclosed a method for constructing and displaying tree structures with automated data processing equipment. A focused view of a portion of the tree is provided to enable an operator to perform editing and evaluating functions on the tree. The focused view presents a view of this portion of the tree structure with a geometry different than what would be used if the entire structure were to be portrayed. This provides a view with sufficient resolution to be highly readable. In the preferred embodiment, the focused view is comprised of a focus node of the tree, its parent node along with the branch connecting the parent node and the focus node, the sibling branches of the connecting branch, all successor nodes of the focus node, and the branches connecting the successor nodes to the focus node.

Abstract: A method for making integrated circuits in which a polyimide/conductor multilevel film is cast on a substrate, using available or existing semiconductor processing equipment. The polyimide film is formed from readily available polyamic acid resins, and the conductor can be sputtered aluminum formed to interconnection conductor patterns by standard photolithographic techniques. After fabrication of the multilayer film, the conductors of the film and the device circuit are brought into aligned contact, and the device circuit affixed to the film. The film and the device are then removed from the substrate for further processing, such as bonding the device and film to a mother board or leadframe, as desired.

Abstract: Spatial light modulators with deflectable metal flaps hinged to conducting posts on a substrate are disclosed. The metal flaps and conducting post may be a single piece, and connected to addressing circuitry in the substrate. Also, plasma etching to fabricate the flaps without breakage is disclosed.

Abstract: A test partitionable logic circuit comprises a plurality of functional modules (26a)-(26n). Each of the functional modules is interfaced with the exterior of the logic circuit with a data bus (20), address bus (16) and a control bus (12). Each of the modules (26) is addressable through an address decode/select circuit (52) to operationally isolate the select modules and define a test boundary. Test data is scanned into a serial chain of shift register latches (SRL's) which are connected in a daisy chain configuration. The defined test boundary allows each of the modules to be separately selected and tested such that the test program for an individual module is separate and distinct.

Abstract: A testable logic circuit includes parallel registers (72)-(80) for interfacing with a common internal bus (70). The parallel registers (72)-(80) are individually addressable by an address decoder (104) for storage of test vectors therein. These test vectors are then applied to associated logic circuits. Individual shift register latches (92)-(102) are provided at imbedded locations therein. The shift register latches are interfaced with a serial data link to allow serial loading of data therein. The parallel latches function in both the test mode to store test vectors for application to the associated logic and also in the operational mode for storage of logic data. Use of parallel registers increases the speed at which data is scanned into the device.

Abstract: A semiconductor device fabrication process comprising the following sequential steps:Sequential formation of an oxide layer and first layer of masking material resistant both to oxidation (particularly preventing the action of oxidants, such as water vapors and O.sub.

Abstract: Disclosed is a method for etching a tin oxide layer (18). The tin oxide layer (18) is masked by selectively forming an etchant-resistant material (20) on it. This material is itself patterned and etched, and then the exposed tin oxide (26) is isotropically etched such that substantially all of the exposed tin oxide (26) is removed. The preferred etchant of the invention comprises a major portion of inert nitrogen gas with a minor portion of hydrogen iodide. A vertical wall reactor (48) is provided for use with the invention in order to achieve a uniform flow and etch rate. In an alternate embodiment, a plasma reactor can be used to perform the etching.

Abstract: In one embodiment of a vertical bipolar transistor constructed in accordance with the teachings of this invention, oxygen is implanted into the vertical bipolar transistor to provide a silicon dioxide layer between the base and collector of the vertical bipolar transistor. This silicon dioxide layer reduces the actual interface area of the base to collector junction, thereby decreasing the capacitance of the base-collector junction. In addition, the dielectric constant of the silicon dioxide layer is such that the capacitance across the silicon dioxide layer, and thus between the base and collector, is minimal relative to the base to collector capacitance provided by the base to collector junction itself. In an alternative embodiment, nitrogen is implanted to form silicon nitride regions rather than silicon dioxide regions.

Abstract: A package for shipping and dispensing articles such as integrated circuit mounting sockets or the like comprises an extruded, open-ended plastic tube having a reentrant rib formed along one tube side so that the interior tube chamber accommodates the bifurcated lateral outlines of such i.c. sockets in side-by-side serial relation to each other inside the tube with the socket bodies resting on the rib and with the socket terminals suspended and protected on either side of the rib.

Abstract: A delay circuit for internal clock generation in a dynamic RAM uses a one-shot multivibrator composed of a pair of cross-coupled CMOS NOR gates with a RC delay circuit in the coupling path between the output of one NOR gate and the input of the other. The RC delay circuit uses an MOS transistor as the resistor, with the gate of this device connected to the supply voltage, so the resistance varies with changes in the supply. A CMOS inverter stage in the delay circuit has its input connected across the capacitor of the RC delay, so the trip point will vary with threshold voltage. In a dynamic RAM, this circuit may be used to establish the critical timing between write and read mode.

Abstract: A passivated dual dielectric gate system compatible with low temperature processing utilizes a dual dielectric system with a silicon dioxide dielectric film or layer at the monocrystalline substrate surface, or termination. The dual dielectric system includes a dielectric film at the substrate surface of thicknesses of from 200 to 1000 .ANG.(or greater ). Respective layers of undoped amorphous silicon and titanium nitride overlie the top of the silicon dioxide and an aluminum gate metal layer overlies the titanium nitride layer. The structure can be patterned by selectively patterning photoresist and a dry or dry/wet etch processses. The structure is patterned and etched as desired.

Abstract: A process, and product made thereby, for bonding two wafers together to form a single wafer with a continuous interface, and for selectively burying a low impedance conductor in the wafer, by providing host and guest wafers having substantially the same crystal orientation and periodicity. A crystalline boundary n-semimetal is formed on the wafers, which are then brought into intimate contact. If desired, a unipolar conductor is fused to one of said wafers. Then, the wafers are exposed to an elevated temperature, or rapid thermal anneal, in an inert ambient, breaking up any native oxides and diffusing any excess oxygen into the wafer lattices. The guest wafer is then mechanically lapped back and chemically etched.A vertical cascode integrated half H-bridge motor driving circuit made in the guest and host wafers has a source transistor in the host wafer with with the wafer substrate forming the collector of the transistor, an isotype acceptor doped Ge.sub.x Si.sub.

Abstract: A motor protector having a thermostat metal element thermally coupled to an electrical motor in a refrigerator compressor motor system has a heater responsive to motor current thermally coupled to the thermostat metal element and has an improved component arrangement to provide locked rotor and ultimate trip protection for the motor without requiring calibration of the operating temperature for the protector after assembly or after incorporation in the motor system.