Abstract: An electronic digital processor system including an internal memory for the storage of data and commands, an arithmetic and logic unit, a register set, data paths and control/timing circuitry together with peripheral control circuitry which provides a number of memory configurations and also provides offset addressing capability to access the interrupt control circuitry, interval timing circuitry and input/output ports. The several memory configurations include configurations that allow for the storage of commands and the storage of data in external devices interfaced to the processor system through the input/output port circuitries.

Abstract: An electronic apparatus with processing capability dedicated to the display function. This apparatus includes a keyboard for inputting data into the processor system and a display for presentation of the output data from the processor system. The electronic digital processor system includes a memory, an arithmetic and logic unit and two central processing units that operate independently and simultaneously. The keyboard input is connected to one central processing unit and the display is connected to the second central processing unit. The algorithm in the first central processing unit is dedicated to obtaining inputs from the keyboard and performing certain operations defined by the function of the apparatus. The algorithm contained in the second central processing unit is dedicated to the display of output data contained in a RAM in the digital processor system. Since both central processing units operate simultaneously and independently, they both use the same locations in RAM.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register (IR) with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort.

Abstract: A method for selective removal of metallization in integrated circuits. A uniform metal film is applied over a patterned resist layer. A short pulse of radiant energy is then applied to the whole surface of the metal film. The resist underneath the metal film is locally heated enough to cause outgassing, which breaks the mechanical bond between the metal film and the resist. The metal film over the patterned resist layer is then removed, leaving the deposited metal film in place over areas which were not covered by the resist film.

Abstract: This system includes an LPC parameter speech synthesizer which basically needs ten binary bits for each LPC coefficient. However, external sources are allowed reduced storage and frame rate requirements by encoding the set of LPC coefficients in a data frame with bit-allocation, repeat-bit, and variable-length features. A three-memory system provides transformation: a speech word selected by controller 11 is transformed by a ROM (30) into an address to a ROM (12 or 13) which outputs corresponding speech data in reduced encoded format to a ROM (202) which converts the coded frame of coefficients to uncoded ten-bit coefficients as needed by the speech synthesizer.

Abstract: A via formation process for HgCdTe (i.e., for pseudo-binary alloys of HgTe and CdTe). Photoresist is patterned on the HgCdTe surface, and ion milling is used to cut holes in the HgCdTe as defined by the photoresist. With this photoresist still in place, the HgCdTe is wet etched to smooth the via walls and expand the via size to a precise dimension.

Abstract: A method of designing and manufacturing a modular integrated circuit for a 4 bit microcomputer family utilizing a modular concept which is adaptable for a variety of applications and specific circuit desgins. The modular circuit is designed as a large block of cells which contains an ALU, instruction decoder, bus structure and a small amount of RAM and ROM as well as ROM control logic. In addition, the block contains attachment points for additional ROM and RAM and for special input/output devices such as I/O bus, timekeeping, A-D, D-A, display drive, communication ports and general purpose control lines.

Abstract: The problem of CdTe sticking to quartz boats is avoided by preventing any presence of cadmium oxides in the as-compounded CdTe. This is accomplished by distilling the cadmium under a high vacuum immediately prior to the CdTe compounding step.

Abstract: A broad band surface acoustic wave (SAW) device has an edge-deposited transducer (EDT) capable of frequencies in excess of 1 GHz and bandwidths in the hundreds of MHz. The device includes a transducer on a semiconductor substrate which is either non-piezoelectric or weakly piezoelectric. The substrate has a sharp, smooth edge formed by the intersection of its top and a side surface. The transducer includes a passivation layer deposited on the side surface of the substrate and a starter layer deposited on the passivation layer; an inner metallic (gold, for example) electrode deposited on the starter layer; a transducer layer deposited on the inner metallic electrode; and an outer metallic electrode deposited on the transducer layer. The outer electrode is formed on the transducer layer one-fifth wavelength below the top surface of the substrate.

Abstract: An electronic learning aid of the type having a keyboard, a display at which problems are posed, a circuit for posing problems at the display, and a circuit for comparing proposed answers entered at the keyboard with correct answers, is provided with a timing circuit for measuring elapsed time while a set of problems is being posed to an operator of the learning aid. The timing circuit is preferably arranged to actuate different segments of a timing character in the display when the timing circuit is performing its timing function. The timing circuit is also preferably arranged to actuate, at the conclusion of a set of problems, the display to provide an indication to the operator of the learning aid the total elapsed time taken in solving the set of problems.

Abstract: A remotely controlled circuit control device has first and second load contact assemblies movable into circuit engagement and circuit disengagement positions relative to one another in which one load contact assembly is operatively connected to a solenoid so that alternate forward strokes of the solenoid moves the one load contact assembly between reset and tripped positions through a push-push mechanism having an indexing portion and a latching portion. An overload mechanism cooperates with the latch portion to cause the load contact assemblies to move to the circuit disengaged position upon occurrence of a fault condition. The second load contact assembly includes pivotably mounted contact members which are linked to the first load contact assembly in such a way that circuit engagement during solenoid energization is precluded.

Abstract: A thermostat device comprises a thermostat unit having a surface which faces in a first direction and which is preferably disposed in thermally-coupled heat-transfer relation to an object whose temperature is to be monitored so that the thermostat unit is promptly responsive to changes in object temperature, the thermostat unit also having other surfaces which face in an opposite direction.

Abstract: A thermostat device comprises a thermostat unit having a surface which faces in a first direction and which is preferably disposed in thermally-coupled heat-transfer relation to an object whose temperature is to be monitored so that the thermostat unit is promptly responsive to an object temperature, the unit also having other surfaces which face in an opposite direction. A metal mounting bracket plate has a base portion, has a stud secured to the base portion to extend in one direction from the base for securing the plate to the object to be monitored in thermally-coupled heat-transfer relation to the object, and has integral spring portions upstanding from respective opposite ends of the base portion of the plate.

Abstract: A remotely controlled circuit control device has first and second load contact assemblies movable into circuit engagement and circuit disengagement positions relative to one another in which one load contact assembly is operatively connected to a solenoid so that alternate forward strokes of the solenoid moves the one load contact assembly between reset and tripped positions through a push-push mechanism having an indexing portion and a latching portion. An overload mechanism cooperates with the latch portion to cause the load contact assemblies to move to the circuit disengaged position upon occurrence of a fault condition. The second load contact assembly includes pivotably mounted contact members which are linked to the first load contact assembly in such a way that circuit engagement during solenoid energization is precluded.

Abstract: An electronic digital processor system including a plurality of processing units with dedicated input port and output port for each of the processing units and an output port that is shared by the processing units. The digital processor system also includes a ROM for the storage of commands, a RAM for the storage of data, an arithmetic and logic unit for performing operations on the data, two independent and simultaneously operable processing units for executing these commands on the data and the control circuit for providing for simultaneous execution of commands in both processing units.

Abstract: An MOS-type VLSI device is made by a process which provides a planar surface yet maintains geometric control for narrow line widths. The field oxide is recessed by etching the surface of a semiconductor body using thick masking for active device areas. Deposition of field oxide with poor step coverage allows the sidewall to be removed, leaving the top of the field oxide at the same level as the original silicon surface. The thick mask areas are lifted off, resulting in a planar oxide-insulated pattern for formation of transistors or N+ conductive lines.

Abstract: An improved electromagnetic relay having a wafer of material with positive temperature coefficient of resistivity (PTC) mounted inside the relay combines a sturdy construction with low manufacturing costs adapting the relay for use as a starting relay for electric motors of compressors. For this purpose, the magnetic members of the relay are incorporated in the electrical relay circuit and are provided with attachments for plug-on connections of the relay to circuit pins of motor-compressor units.

Abstract: A bar code reader is sensitive to at least three levels of darkness. At least three levels of darkness are utilized in the bar code so that, a higher density of data is thereby achieved. In the preferred embodiment, the bar code is encoded so that a transitional change from one level of darkness to another level of darkness is indicative of the data bits encoded. The bar code reader is passed over the multilevel bar code and through the use of a linear conversion such as by an analog to digital converter, the level of darkness of the bar is communicated to a decipher so as to be translated into a binary sequence.

Abstract: An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process, modified to include a P-channel transistor. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. Field oxide is grown after the N-type tank is formed. A polycrystalline silicon layer is deposited and patterned to create gates for both N- and P-channel transistors, then separately masked P- and N-type diffusions or implants form the sources and drains for the two types of transistors.

Abstract: A high-voltage CMOS process, providing (for 5 micron geometries) both field thresholds and junction breakdowns in excess of 20 volts, wherein only one channel stop implant is used. A double-well process in an epitaxial structure is used. Phosphorus is preferably used as the dopant for the N-tank, and boron is used for the blanket channel stop implant. The boron tends to leach into oxide, and the phosphorus tends to accumulate at the surface, and a high field threshold is achieved over both PMOS and NMOS regions.