Abstract: A carrier having a plurality of leads extending from the lateral sides thereof. The leads extend along the lateral side and over protuberances into depressions in the bottom of the carrier. Each of the depressions is separated by ribs from the other depressions. The ends of the leads disposed in the depressions are prevented from substantial movement by the rib to prevent contact with adjacent leads. At least some of the leads are provided with holes disposed adjacent to the exit of the leads from the enclosure of the carrier. The holes in the leads allow the leads greater flexibility at their portions close to the entrance of the leads into the enclosure. The leads are tapered along their length toward the protuberances. Further, the leads are separated by a width along the lateral side which is within the range of substantially the width of the leads to less than the width of the leads to prevent nesting.

Abstract: A fuel system for an internal combustion engine has an electrical resistance heater accommodated in low profile gasket means at a location between a throttle body mounting flange and a mating intake manifold flange for heating the throttle body. The gasket means comprises a relatively rigid electrically insulating spacer forming a chamber, a heat-transfer member and a terminal secured to opposite sides of a heater for mounting and making electrical connection to the heater which is accommodated in the spacer chamber, and relatively thin outer layers of more compressible gasket material for sealingly engaging the throttle body and mating manifold flange means respectively.

Abstract: Disclosed is a pulsed FM receiver with automatic centering of the intermediate frequency at the true center of the input filter passband. The frequency standard of the frequency discriminator which controls the local oscillator frequency is adjusted to produce zero discriminator output during the period between signal pulses. The discriminator frequency standard remains automatically aligned with the center of the input filter passband and the input bandwidth may then be reduced for optimum receiver sensitivity.

Abstract: A didactic device for providing a learning experience and/or entertainment by serving as a learning aid to improve penmanship and drawing skills. The didactic device combines an optical image processing system with a speech synthesis system, wherein a drawing surface is provided in registration with the field of view of an optical imager. The user of the didactic device is requested either visually via a display mounted on the housing of the didactic device in proximity to the drawing surface or verbally via speech synthesis electronics to write or draw something on the drawing surface. When the user has completed the assignment by drawing indicia on the drawing surface, the image processing system, which includes an imager chip, a matrix memory in which signal data output from the imager chip is stored, and a data processor having an object recognition comparator, is actuated.

Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word lines and the gates of the access transistors are formed by the metal strips. No metal-to-silicon or metal-to-polysilicon contacts are needed. The access transistors are made by etching through polysilicon strips which are the capacitor bias plates. The size of the transistor is not determined by alignment accuracy.

Abstract: A fuel system for an internal combustion engine has an electrical resistance heater accommodated in gasket means disposed between a throttle body flange and a mating flange on an intake manifold so that the heater is located immediately adjacent an idling speed fuel inlet nozzle or the like in the throttle body for transferring heat to the nozzle area through the throttle body flange to prevent freeze-up of the nozzle during engine operation.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. For a given set of addresses parallel data transfers occur and for a different set of addresses serial data transfers occur. A single instruction may transfer one bit, multiple bits in series, or bytes or words in parallel; the serial or parallel mode is specified by the address, so software may be written without regard for the type of interface. This serial/parallel I/O port shares the address/data bus with memory and may be used with any memory-mapped peripheral.

Abstract: A microwave voltage-controlled oscillator includes a varactor-controlled tuned circuit connected to the gate of an FET. The gate of the FET forms a Schottky barrier contact with the channel region. This Schottky barrier operates to clip the RF voltages generated in the gate circuit, and this clipping is used to provide the necessary gate bias to set the operating point of the VCO. No other source of bias is provided, and thus no DC return path from the gate circuit to the source or drain of the FET exists. Thus, the other circuit elements normally required to establish the gate operating point, which would have high frequency resonances, are eliminated. This permits operation of a microwave VCO over an extremely broad bandwidth.

Abstract: Controllable doping of HgCdTe in concentrations low enough to be useful for electronic devices is accomplished by dissolving the desired dopant in mercury at or below the solubility limit. The mercury is then diluted with pure mercury, to lower the dopant concentration to that which will produce the desired impurity concentration in the end product. The doped mercury is then compounded according to conventional methods, to produce reproducibly doped HgCdTe of uniform composition.

Abstract: A method for the fabrication of microelectronic semiconductor circuits, including the concurrent low pressure deposition of monocrystalline and polycrystalline semiconductor material in a predetermined pattern. In a preferred embodiment, a dielectric isolated circuit is fabricated, by such selective epitaxial growth, and a subsequent oxidation of both the mono- and polycrystalline deposits. By controlling the ratio of the deposition rates, and by controlling the oxidation step, the poly deposit is substantially fully converted to oxide, while the mono is only partly oxidized, leaving a substantially coplanar, isolated matrix of passivated monocrystalline areas in which to fabricate circuit components for interconnection.

Abstract: A remotely controlled circuit control device has first and second load contact assemblies movable into circuit engagement and circuit disengagement positions relative to one another in which one load contact assembly is operatively connected to a solenoid so that alternate forward strokes of the solenoid moves the one load contact assembly between reset and tripped positions through a push-push mechanism having an indexing portion and a latching portion. An overload mechanism cooperates with the latch portion to cause the load contact assemblies to move to the circuit disengaged position upon occurrence of a fault condition. The second load contact assembly includes pivotably mounted contact members which are linked to the first load contact assembly in such a way that circuit engagement during solenoid energization is precluded.

Abstract: A surface mounted integrated (IC) device package or carrier is disclosed suitable for accommodating large terminal count IC devices in a small space. A carrier, preferably of plastic, is disclosed having notches or castillations in its sides. A first row of leads are positioned in the periphery of the package and a second row of leads are positioned in the notches, said notches formed a predetermined distance from the periphery of the package (e.g., 0.050"). Selected leads of the second row are alternated with said first row of leads. In the preferred embodiment, the first and second leads are separated by 0.025". Also in the preferred embodiment, the first and second row of leads extend over protuberances into depressions in the bottom of the package. Each of the depressions is separated by ribs from the other depressions such that the ends of the leads are disposed in the depressions and are prevented from substantial movement, thereby preventing contact with adjacent leads.

Abstract: A method for etching tapered apertures in the insulating layer between metal layers in an integrated circuit having a multilevel interconnection system. In one embodiment a thin layer of polysilicon is formed on the interlevel oxide layer followed by deposition of a photoresist layer thereon. A pattern of apertures is formed in the resist layer which is then exposed to a selective silicon etchant to form an opening in the polysilicon layer extending to the surface of the oxide layer. The polysilicon and oxide layers are then etched with a nonselective etchant. During the oxide etch the polysilicon is etched laterally, thereby widening the apertures and producing a taper in the aperture sidewalls as the etch proceeds. The magnitude of the taper is related to the thickness of the polysilicon layer. In another embodiment wherein the oxide layer directly overlies a silicon region, the polysilicon and oxide layers are first exposed to a nonselective etchant to etch partially through the oxide layer.

Abstract: A system and method for controlling the effective root mean square (RMS) voltage (Veff) across the segments of a liquid crystal display as a function of the frequency of the voltage signal applied thereto and selected parameters of the display package are described. Display parameters such as the thickness of the barrier dielectric layer and the electrical resistance of the liquid crystal material are chosen so that the ON and OFF states of the display are selectively controllable by lowering the frequency of the drive voltage signal applied to the OFF segments (Foff) a predetermined amount below that of the drive voltage signal applied to the ON segments (Fon), thereby decreasing the ratio of the effective RMS voltage Veff to the RMS voltage of the applied voltage signal (Vapp) for the OFF segments as compared to the ratio Veff/Vapp for the ON segments. The number of drive lines which can be effectively multiplexed is thereby increased.

Abstract: A rectifier/multiplier/level shifter utilizing multiple capacitors which are switched from parallel to series or vice versa. An analog signal is communicated to a plurality of capacitors in parallel which are subsequently connected in series by selective switching. Depending upon the sign of the analog signal, taps are made on the capacitors so as to rectify the incoming analog signal. In a similar fashion a tap utilizes the serial multiplication of the capacitors so as to create a multiplier circuit. This particular architecture is particularly well suited for a metal-oxide-silicon (MOS) embodiment.

Abstract: An improved thermally actuated valve assembly having a double throw feature comprises three ports in which two passage routes are provided through the valve; one passage route connecting ports one and two and the other passage route connecting ports two and three. A snap acting strip type bimetallic member vertically mounted in the valve serves as a thermal element and valve member to cause a change in communication from one of the passage routes to the other.

Abstract: A microcomputer system has a microprocessor whose functions are implemented by instructions and data from a directly connected random access memory (RAM). The capacity of the RAM is less than the typical total instruction list for the microprocessor. A read-only mass memory is connected to the RAM and has permanently stored instructions set therein for the microprocessor. A controller controls the flow of instructions from the mass memory to the RAM as required and also controls the flow of instructions and data between the RAM and microprocessor. The instructions from the mass memory are overlayed in the RAM in areas no longer required for instruction execution.

Abstract: A thermal or pressure responsive switch has a contact arm movable between switch positions opening and closing switch contacts, has a spring biasing the arm to one of the switch positions, and has a dished disc element movable with snap action between original and dished configurations during changes in pressure or temperature conditions. The dished disc element cooperates with the spring in moving the contact arm between switch positions on the occurrence of selected switch actuating or reset pressure or temperature conditions, and the switch components are arranged to permit overtravel of the disc during snap acting movement for closing switch contacts without substantially altering the pressure or temperature response characteristics of the switch.

Abstract: A microcomputer device is disclosed containing a ROM for program memory, a read/write memory, and a CPU in a single integrated circuit. Input/output ports, interrupt and operating mode controls are memory mapped in the same logical address space as the program and read/write memory. The read/write memory is an array of one-transistor type dynamic storage cells in which data bits are stored in capacitor; refresh of this dynamic RAM is accomplished in a manner transparent to the CPU by an automatically-incremented address counter. Each data bit uses two one-transistor cells in a balanced, complementary array.

Abstract: Non-volatile JRAM cell having interelectrode non-volatile capacitance which is readable and varies with the electrical charge on elements of the device. To program the nonvolatile capacitance, the address lines (word line and bit line) are biased so that a charge is given to the nonvolatile multidielectric stack between the MIS gate and the JFET source of the cell. For a charge of one polarity, an inversion layer of electrons (for a P-type substrate) is formed on the surface of the JFET source, increasing the capacitance between the MIS gate electrode and the JFET gate electrode. For the opposite polarity, an accumulation layer forms at the JFET source surface, decreasing the interelectrode capacitance. The cell is read by presetting one address line, floating that line, then putting a pulse on the other line while reading the voltage output on the floating line.