Abstract: A high-voltage CMOS process, providing (for 5 micron geometries) both field thresholds and junction breakdowns in excess of 20 volts, wherein only one channel stop implant is used. A double-well process in an epitaxial structure is used. Phosphorus is preferably used as the dopant for the N-tank, and boron is used for the blanket channel stop implant. The boron tends to leach into oxide, and the phosphorus tends to accumulate at the surface, and a high field threshold is achieved over both PMOS and NMOS regions.

Abstract: An adaptive filter suitable for speech analysis which is constructable on a silicon chip. The filter has a single multiplier and a single adder in series together with appropriate registers or memories so that the output of the adder is either looped back to the adder itself or alternatively is looped, after a delay, to the multiplier so as to perform the operations of an all-zero digital lattice filter in computing a moving average, employing linear predictive coding. Another register provides the multiplier with the constant values typically associated with lattice filter coefficients. Preferably the multiplier is an M-stage pipeline multiplier so as to reduce the area necessary for its incorporation on a silicon chip. The filter accepts digital samples of the voice input and outputs a compressed data representation of the input.

Abstract: A memory system for a digital processor device having a 16-bit bidirectional bus with multiplexed addresses and data employs separate memory devices for the high order and low order data bytes. When less than 64K words of memory are used, there are unused address lines in the bus. A microcomputer may use memory devices partitioned 4K.times.8, needing 12 address pins. Both devices are constructed the same, but one accesses the low order byte and the other the high order byte under control of a single byte-select terminal. Mapping of the bus to memory device connections and internal connection of unused pins to address inputs or data input/output lines within the memory devices, along with the byte-select function, allow a single type of device to function in either position.

Abstract: A data processing system having separate read-only memory and read-write memory integrated circuits coupled to a central processing unit via the same interface system. The data processing system is comprised of bus means having either command, address, or data signals present and conducted thereon. In the preferred embodiment, the bus means is comprised of a four binary digit bidirectional conductor bus coupling between the central processing circuit and the memory circuits.

Abstract: An electronic learning aid for interactive operation with an operator with capabilities for the synthesis of a tone or sequence of tones. The tone, in the alternative, is used to either prompt the operator to respond in like fashion or is in response to the operator's input of a tone or sequence of tones. In this fashion the learning aid selects a tune to be synthesized and communicates this tonal sequence to the operator who responds by attempting to mimic the sequence. An alternate operation of the learning aid is for the operator to audibly input a tone sequence and for the electronic learning aid to attempt to mimic the sequence of tones.

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by an improved process employing selective oxidation of polysilicon using PN junction capacitors. A relatively flat surface results from the process, which is favorable to patterning small geometries. The PN junction storage capacitors have improved alpha particle protection. Metal-to-polysilicon gate contacts are made at silicide areas over polysilicon gates; the silicide lowers resistance of the poly elements.

Abstract: A light modulator comprising a light-reflective metallized membrane defining a deformable mirror disposed over a semiconductor substrate of one conductivity type in which a matrix array of field effect address transistors are formed, the metallized membrane cooperating with a matrix of floating metallic field plate members disposed on an insulating layer covering the substrate to define an array of air gap capacitors for line addressing by the field effect address transistors. The floating metallic field plates are opaque to light and prevent photocharge generation in the active regions of the matrix array of field effect address transistors. The metallized membrane is spaced from the field effect address transistors and the metallic floating field plates by an upstanding semiconductor grid structure which is formed on the insulating layer of the semiconductor substrate and defines gate electrodes for the address transistors.

Abstract: A method for producing AC-driven thin film electroluminescent displays, wherein the phosphor is laser annealed to enhance crystallinity. Preferably the phosphor is zinc fluoride, which has a relatively low melting point, facilitating low temperature processing.

Abstract: An electronic digital processor system including an internal memory, an arithmetic and logic unit, registers, peripheral control circuitry providing an internal mode, an external mode, emulator mode, data paths, and control and timing circuitry. In the internal mode, the data and the commands are stored in the internal memory. In the external mode, the commands which control the operations of the microcomputer are stored in the external memory. In the emulator mode, the user can combine the microcomputer with external devices to emulate a composite system with minimal hardware. The emulator mode would also allow the user to develop software for the composite system.

Abstract: Speech synthesis system implementable in an integrated circuit device capable of converting frames of speech data at a variable frame rate into analog signals representative of human speech. The frames of speech data comprise digital representations of values of pitch, energy, filter coefficients and coded frame rate data. The speech synthesis system includes a linear predictive coding filter as a speech synthesizer which utilizes the speech data at a varying frame rate to produce digital speech signals representative of human speech. Frames of digital speech data including coded frame rate data are received by an input, with the frame rate data being decoded to control both the rate at which the incoming variable-length frames of speech data are accepted by the speech synthesizer and the number of interpolation calculations required to define interpolated speech values between adjacent incoming frames of speech data.

Abstract: Apparatus and method for cleaning material at the outer edge of an object by applying a fluid, which can be a solvent, for the material to a flat surface adjacent the edge by contact and moving the solvent onto the edge by centrifugal force. A slot is provided in a planar surface. The slot is filled with solvent for contact with the flat surface of the object. The slot is arcuate and elongated. The fluid is directed along the slot in the direction of rotation by a baffle. The slot has a bottom sloping upward toward the planar surface in the direction of rotation. A notch is provided between an edge of the planar surface and the slot to act as a spillway for excess solvent.

Abstract: An electronic learning aid in which the student supplies a problem to which the learning aid supplies a response. The response of the learning aid is sometimes correct and at other times incorrect, thus requiring the operator/student to respond as an educator of the learning aid. This educating of the learning aid by the student requires the ability to recognize the correct answer. Preferably, if the student recognizes the correct response, praise is given; otherwise, either the problem is explained to the student or the learning aid ventures another guess. This "educating" of the learning aid through the posing of problems from the operator allows the student to proceed at his own pace and yet tries the limits of his knowledge.

Abstract: Apparatus and method for cleaning material at the outer edge of an object by applying a fluid, which can be a solvent, for the material to a flat surface adjacent the edge by contact and moving the solvent onto the edge by centrifugal force. A slot is provided in a planar surface. The slot is filled with solvent for contact with the flat surface of the object.

Abstract: A printhead configured to thermally print on thermally sensitive paper when traveling in either a forward or reverse direction across the paper. The substrate on which the thermal printhead is supported is especially configured to minimize drag between the printhead structure and the paper while traveling in either direction. As a result the travel dynamics of the printhead and the voltages required to insure uniform printing by the printhead are substantially independent of whether the printhead is traveling in a forward or reverse direction relative to the paper. The printhead may be mounted directly on a metallic substrate to increase heat dissipation and permit high speed printing.

Abstract: An integrated circuit (IC) device package is disclosed suitable for accommodating large terminal count IC devices in a very small space. A first set of terminals is located in notches around the periphery of the package. A second set of terminals is located inboard of the package and are comprised of metallized annular rings on the top and bottom surfaces of the package around holes or apertures through the surfaces of the package with metallization coating the holes to connect the top and bottom annular rings. This second set of terminals may be arranged in rows parallel to the edges of the package and may be connected to the IC device through buried conductor traces and wire bonding techniques. If necessary, additional rows of metallized holes can be utilized in a grid configuration, preferably at 0.050" centers.

Abstract: A communications link having a position capability responsive to either a manual or remote control actuation. In one embodiment, a remote carrier has a navigation system for outputting signals representative of the carrier location or position. A frequency shift key (FSK) modulator is connected to the navigation system for tone coding the carrier position signals, a transmitter of a transceiver is connected to the modulator for transmitting the carrier position signals, and a position enable switch for controlling selectively the transmittal of the carrier position signals.

Abstract: A method of allocating memory space on a cyclic memory system is described. The memory system is partitioned into a plurality of memory regions with each of the regions containing contiguous memory elements. Each of the memory regions is then partitioned into a plurality of memory subregions wherein all subregions within a region are of equal memory capacity but where subregions of different regions have different memory capacities. A file of data is then assigned to occupy one available subregion of the memory which is the smallest available subregion which has sufficient memory capacity to contain the file of data.

Abstract: A non-volatile JRAM cell is constructed to require only positive voltage for programming and erasing of data in the cell. The "well" region of the cell JFET device may be implanted with an impurity concentration that will permit lower breakdown voltage or the non-volatile gate may overlap the JFET gate sufficiently to be able to have the same effect, or some combination of both may be used. This allows the cell to be erased using voltages of one polarity.

Abstract: A data processing system having a large slow main memory and having a small fast memory is disclosed with means for allowing slow memory calls to fast memory routines and means for allowing returns from programs executing in the fast memory so as to return to program execution in the slow main memory. Also disclosed is circuitry for selectively deactivating the main memory and for selectively activating the fast memory responsive to particular ones of data signals output from the main memory, and means for selectively deactivating the fast memory and for selectively deactivating the main memory responsive to predefined ones of data signals output from the fast memory, thereby allowing program calls embedded in the slow main memory to transfer execution control to the fast memory, and providing retransfer of execution control from the fast memory to the slow main memory in response to a RETURN code embedded in the fast memory.

Abstract: A nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix pattern and means for sensing data stored in said memory cells, characterized in that each of said memory cells comprises a pair of symmetrical submemory cells, and the pair of said submemory cells can store logic states opposite to each other.