Patents Assigned to Texas Instruments
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Patent number: 4458777Abstract: A vibratory seismic energy source capable of generating significant energy over a broad frequency band. The vibrating baseplate and associated structure are designed to have minimum weight while still retaining sufficient structural integrity to permit the use of high actuator forces. This, coupled with a large reaction mass results in the generation of significant energy levels in the earth at high frequencies.Type: GrantFiled: February 22, 1982Date of Patent: July 10, 1984Assignee: Texas Instruments IncorporatedInventors: Richard M. Weber, John W. Bedenbender
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Patent number: 4459565Abstract: A low current electronic oscillator system includes an oscillator tuning element, such as a piezoelectric crystal, operable at a predetermined frequency and an oscillator control circuit for cooperating with the tuning element to provide an oscillating electrical signal at the predetermined frequency. The control circuit includes first and second electrical charge storage devices coupled to a first portion of the tuning element; a first current drive device connectable to a first terminal of an applied electric potential and responsive to a first voltage on the first charge storage device for applying a first drive current to a second portion of the tuning element; and a second current drive device connectable to a second terminal of the electric potential and responsive to a second voltage on the second charge storage device for applying a second drive current to the second portion of the tuning element.Type: GrantFiled: September 13, 1982Date of Patent: July 10, 1984Assignee: Texas Instruments IncorporatedInventor: Jerald G. Leach
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Patent number: 4457066Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word address lines and the bias lines for the capacitors are formed by metal strips. The gates of the access transistors and the capacitor gates are polysilicon. Metal-to-polysilicon contacts are made to connect the metal word lines to the polysilicon gates of the access transistors and to connect the metal bias lines to the capacitor gates.Type: GrantFiled: October 15, 1980Date of Patent: July 3, 1984Assignee: Texas Instruments IncorporatedInventors: G. R. Mohan Rao, Donald J. Redwine
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Patent number: 4458231Abstract: A motor protector having a thermally and electrically conductive housing with a closed end and an opened end and defining a switch cavity therein is hermetically sealed with a header assembly. The header assembly has an outer margin circumscribing a central electrically insulative glass portion through which extends an electrically conductive terminal pin. A thermostatic assembly is mounted on the distal free end portion of the pin within the cavity and includes a heater element which extends from the pin toward the closed end of the housing. A snap-acting thermostatic element is cantilever mounted to the heater intermediate the ends of the heater and has a movable contact disposed on the distal free end thereof. A stationary contact is disposed within the cavity and is physically and electrically connected to the housing adjacent the closed end thereof on a relatively flat shelf formed in the wall of the housing.Type: GrantFiled: December 14, 1981Date of Patent: July 3, 1984Assignee: Texas Instruments IncorporatedInventor: Ronald E. Senor
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Patent number: 4458339Abstract: A method of seismic prospecting is disclosed in which the seismic source is excited in such a manner as to maximize the use of the energy generated by the seismic source. In certain cases it may be desirable to convert the received seismic signals to their frequency domain counterparts before performing subsequent processing. Such conversion may be performed using the discrete Fourier transform with the result that transformed values are obtained only at certain discrete frequencies. It may further be desirable that processing be performed only at subsets of the total set of discrete frequencies with the values at the remaining frequencies being discarded. In the practice of the present invention, source energy is generated only at those discrete frequencies at which subsequent processing is to be performed. As a result there is substantially no source energy in the transform values at the frequencies which are discarded.Type: GrantFiled: October 6, 1980Date of Patent: July 3, 1984Assignee: Texas Instruments IncorporatedInventor: Cameron B. Wason
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Patent number: 4457719Abstract: Disclosed is an electronic learning aid having modes of operation to provide an interesting and effective learning experience to a student. In the preferred embodiment, inputs to the learning aid are effected via scanning of a bar code on a page by the student. In a first mode, the student is audibly directed to place depicted objects on the page in some specific sequence, as by alphabetical order of the first letter of the names of the objects. The student selects items in the sequence by scanning bar code associated with each item and the system audibly informs him of his progress in correctly identifying times of the sequence. In a second mode the student upon scanning the bar code associated with a depicted object is audibly directed to spell the name of that object. The system audibly informs him of his progress.Type: GrantFiled: May 25, 1982Date of Patent: July 3, 1984Assignee: Texas Instruments IncorporatedInventors: Ashok Dittakavi, Barbara J. Thompson
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Patent number: 4458237Abstract: An analog to digital converter is provided which includes a binary weighted capacitor array connected with a series of resistors structured as an array. The converter provides for charge correction to compensate for any capacitance deviation in the capacitor array. The converter includes a charge redistribution sequence under the control of a microcomputer to determine the digital value of the analog input using the resistor array to determine the least significant bit positions of the analog input. This same resistor array is also used to correct for capacitor value deviations in the binary weighted capacitor array.Type: GrantFiled: November 3, 1981Date of Patent: July 3, 1984Assignee: Texas Instruments IncorporatedInventor: John C. Domogalla
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Patent number: 4458334Abstract: A magnetic bubble domain memory device is provided that includes a magnetic bubble domain data chip having a major/minor loop organization in which one or more defective minor loops may be tolerated. Information in the form of a redundancy map is stored within the plurality of minor loops in a single page thereof, where a page is defined as one bit of information from the same virtual position on each of the plurality of minor loops. This redundancy map comprises firmware wherein the presence of a magnetic bubble domain within the designated page at a specified bit position identifies the particular minor loop corresponding to that bit position as a good loop, and conversely the absence of a bubble within the page at a specified bit position identifies the particular minor loop corresponding to that bit position as a defective loop.Type: GrantFiled: May 16, 1977Date of Patent: July 3, 1984Assignee: Texas Instruments IncorporatedInventor: James B. Hall
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Patent number: 4458163Abstract: A programmable logic device is disclosed which contains additional circuitry allowing the architecture to be programmed. Operating as an input circuit or as an output circuit, the logical function of the device is selected to operate as a buffer, latch or register. When fabricated as a portion of a programmable logic array, the architecture is modified to the desired configuration by fusible connections which conduct normal operating current until overloaded by selective programming. Thereafter, the data path through the array is programmed in a normal fashion. The programmable architecture circuitry is readily fabricated in an integrated circuit form in conjunction with a programmable logic array.Type: GrantFiled: July 20, 1981Date of Patent: July 3, 1984Assignee: Texas Instruments IncorporatedInventors: Glenn Wheeler, James F. Ptasinski
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Patent number: 4455738Abstract: A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is self-aligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.Type: GrantFiled: December 24, 1981Date of Patent: June 26, 1984Assignee: Texas Instruments IncorporatedInventors: Theodore W. Houston, Al F. Tasch, Jr., Henry M. Darley, Horng S. Fu
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Patent number: 4455739Abstract: Gates of individual devices on a slice are connected through a resistance to the device substrate, and through the same resistance to other device gates. This interconnection and high-resistance drain gives the gate protection from static charge buildup and subsequent catastrophic discharge which would result in a faulty device. This method protects each gate from the time of deposition to final device packaging.Type: GrantFiled: April 19, 1982Date of Patent: June 26, 1984Assignee: Texas Instruments IncorporatedInventor: Jaroslav Hynecek
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Patent number: 4456961Abstract: A coordinate system transformation control system for a programmable manipulator having a base referenced by a three dimensional cartesian coordinate system (base frame) includes a hand-held application module for directing the operation of the programmable manipulator. The end effector of the manipulator may be moved to locate a point of origin, a point in the x axis and a point in the x-y plane of another three dimensional cartesian coordinate system (user frame). Other user frames may be selected in the same manner and one user frame may be referenced to another user frame through a mathematical operation. These are known as stacked user frames, all such frames being ultimately referred back to the base frame for operation of the programmable manipulator.Type: GrantFiled: March 5, 1982Date of Patent: June 26, 1984Assignee: Texas Instruments IncorporatedInventors: Robert B. Price, David L. Jones
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Patent number: 4456965Abstract: A data processing system having a bus system for data communication employs a bus splitting circuit. This bus splitting circuit permits selective connection and isolation of individual buses of the bus system. A more flexible assortment of data communications paths among logic blocks coupled to the bus system is permitted by this arrangement in which some logic blocks may be coupled during one state of the bus splitting circuit and decoupled during the other state of the bus splitting circuit. By separating some of the buses via the bus splitting circuit, dual data transfers using the split buses is possible. In a preferred embodiment at least one of the logic blocks is a memory which is coupled to more than one of the buses, thus permitting simultaneous read and write operations, dual read operations or dual write operations.Type: GrantFiled: October 14, 1980Date of Patent: June 26, 1984Assignee: Texas Instruments IncorporatedInventors: Warren S. Graber, Ashok H. Someshwar
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Patent number: 4454591Abstract: An external I/O pull down latch and a system embodiment thereof. The interface system has a bus line including of a first means for providing an output at a fixed voltage level on said bus line for a first time interval, and a second means coupled to said bus line for maintaining the bus line at the fixed voltage level subsequent to the first time interval. In the preferred embodiment, the second means is comprised of said external I/O pull down latch. The present invention is a replacement for traditional pull up or pull down resistors in controlling I/O bus lines coupling main processor circuits with external memory circuits. In the preferred embodiment, the external I/O pull down latch is comprised of a read-write memory bit cell, sized such that it may be overdriven by any driver attached to the bus line.Type: GrantFiled: May 29, 1980Date of Patent: June 12, 1984Assignee: Texas Instruments IncorporatedInventor: Perry W. Lou
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Patent number: 4451968Abstract: A method and device are disclosed which allows an ohmic electrical contact with P-type semiconductor material using metallic foil at low temperature without significant diffusion of the metal into the semiconductor. The contact exhibits opposition to physical separation and has a predetermined electrical resistance.Type: GrantFiled: September 8, 1981Date of Patent: June 5, 1984Assignee: Texas Instruments IncorporatedInventors: Millard Jensen, Jules D. Levine
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Patent number: 4453258Abstract: An integrated circuit automatic gain control circuit maintains an alternating input signal at a predetermined amplitude. A ladder network of capacitors and accompanying FET switches provides for varying the gain of an integrated switched capacitor filter. The output signal from the filter is compared in a comparison circuit, the comparison circuit providing an UP signal if the output signal is too small or a DOWN signal if the output signal is too large. The UP and DOWN signal is applied to a ROM which causes a counter to count up or down in response to the UP or DOWN input signal, the counter inputting the ROM to provide control signals from the ROM for controlling the switches of the capacitor ladder network.Type: GrantFiled: June 2, 1981Date of Patent: June 5, 1984Assignee: Texas Instruments IncorporatedInventor: Donald C. Richardson
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Patent number: 4450843Abstract: A compact, miniature instrument for providing biofeedback information of interest to a user. The instrument is comprised of a wrist-watch size unit, which includes a temperature sensor for sensing the user's external skin temperature and a finger-mountable unit, which includes a heart beat sensor for sensing the user's heart beat. Processing circuitry is provided for computing various biofeedback parameters of interest to the user, including pulse rate, time rate of change in pulse rate and time rate of change in external skin temperature. Timekeeping circuitry is provided for keeping track of various time-related parameters, such as time of day and calendar date. A display is provided for selectively displaying biofeedback and time-related information to the user.Type: GrantFiled: November 24, 1980Date of Patent: May 29, 1984Assignee: Texas Instruments IncorporatedInventors: George M. Barney, Paul R. Michaelis
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Patent number: 4450928Abstract: A dual mode vibrator (DMV), in its hydraulic cylinder, automatically provides a shorter stroke for higher frequencies and a longer stroke for lower frequencies. The cylinder contains a pair of sleeves, each sleeve having one diameter portion sufficient to slideably engage the piston and having a smaller diameter portion to slideably engage the piston rod. The sleeves themselves are moveable within the cylinder, such movement being effected by the application of high pressure on one end or the other. When the sleeves are moved together, the stroke is effectively shortened. When the sleeves are moved apart, the stroke is effectively lengthened.Type: GrantFiled: August 3, 1981Date of Patent: May 29, 1984Assignee: Texas Instruments IncorporatedInventors: Richard M. Weber, John W. Bedenbender
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Patent number: 4451821Abstract: Error correction circuitry for an analog to digital converter is disclosed which provides for the correction of charge in a charge redistribution converter architecture. This conversion technique as implemented requires that a binary weighted capacitor array be present where the capacitors are accurately binarily weighted in decreasing value. The charge correction circuitry allows for the correction of any deviations of binary weighted capacitance value by adding or subtracting charge from the capacitor array. This is accomplished by the use of a resistor array connected to a capacitor that is equal in capacitance to the smallest capacitor in the capacitor array. The converter includes a microcomputer which determines the charge error for each of the individual capacitors together with the total charge error for the capacitive array coupling with the comparitor.Type: GrantFiled: November 3, 1981Date of Patent: May 29, 1984Assignee: Texas Instruments IncorporatedInventor: John C. Domogalla
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Patent number: 4450042Abstract: A plasma etch chemistry which allows a near perfectly vertical etch of silicon is disclosed. A Cl-containing compound such as BCl.sub.3 has Br.sub.2 added to it, readily allowing anisotropic etching of silicon. This is due to the low volatility of SiBr.sub.4. The silicon surface facing the discharge is subjected to ion bombardment, allowing the volatilization (etching) of silicon as a Si-Cl-Br compound. The Br which adsorbs on the sidewalls of the etched silicon protects them from the etching. This new plasma etch chemistry yields a very smooth etched surface, and the etch rate is relatively insensitive to the electrical conductivity of the silicon.Type: GrantFiled: July 6, 1982Date of Patent: May 22, 1984Assignee: Texas Instruments IncorporatedInventor: Andrew J. Purdes