Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

Abstract: An apparatus for incorporating a metallic foil into a semiconductor package includes a carrier embossed with a multiplicity of cavities. Each of the cavities define a pedestal recessed with the cavities which penetrate only partially through the thickness of the carrier. A metallic foil overlying a pattern with the pedestals in direct contact and help support the metallic foil with the metallic foil pressed into at least some of the cavities. In other embodiments, a gap is between the metallic foil and bottoms of the cavities in a substrate. Integrated circuit dice are attached to the foil. Each die is attached to the foil in a region of the foil overlying a portion of the at least one device area pattern. Bonding wires electrically connect the integrated circuit dice to the foil.

Abstract: In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. When the read address is identical to the write address stored in the pipelined memory, the result of a bit-wise ANDing of data stored in pipelined synchronous data registers and data stored in pipelined synchronous bit-wise registers is presented at the output of the multi-port register file.

Abstract: A method for joining integrated circuit (IC) die. The includes pressing the IC die toward a workpiece so that a protruding bonding feature is inserted into a cavity of a receptacle through an opening. The pressing bends peripheral shelf regions downward into the cavity and towards sidewall portions of the receptacle to form bent peripheral shelf regions. A protruding bonding feature contacts the bent peripheral shelf regions along a contact area. The contact area being at least primarily along the sidewall surfaces of the protruding bonding feature.

Abstract: In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. Which bits of data from a pipelined synchronous data register are written into the multi-port register file is determined by a pipelined synchronous bit-write register. The output of the pipelined synchronous bit-write register selects which inputs of multiplexers contained in registers in the multi-port register file are stored.

Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

Abstract: Systems and methods of dynamic current limit are disclosed herein. A current is sensed a wireless charging circuit, for example. When the current sense reaches a reference current level while a communication is active, the current limit is enabled for the next packet. The current limit signal may be cleared for the next packet.

Abstract: One embodiment includes a preamplifier system. The system includes a reference stage configured to set a magnitude of a clamping voltage for a reference node based on a reference current generated in an adjustable reference current path. The system also includes an output stage comprising an adjustable slew current source that is configured to provide an activation current to the reference node in response to at least one activation signal, the output stage to generate an output current at an output of the output stage with a magnitude that is based on the clamping voltage.

Abstract: Echo cancellation is provided in a telephone device by calculating a metric value indicative of a similarity between a representation of an incoming signal from a far end talker and a representation of an outgoing signal from a near end talker. A threshold value is derived based on the metric value. A portion of the outgoing signal is removed by using the threshold value to determine an amount to remove from the outgoing signal with continuous, real-time updating of the threshold value.

Abstract: An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

Abstract: A method of dynamically switching voice channels between sampling rates in a telecommunication system including a plurality of conferenced channels that have a telephony side, a network side, and a conferencing unit therebetween. During conferencing the presence of a switching stimuli is detected, and at least a first affected voice channel affected by the switching stimuli is identified from the plurality of conferenced voice channels. Responsive to the switching stimuli, based on a telephony side sampling rate of the first affected voice channel, a network side sampling rate of the first affected voice channel, and respective sampling rates of other conferenced voice channels, it is determined whether or not to switch a sampling rate for at least the first affected voice channel using a switching criteria. Provided the determining decides to switch, the sampling rate is switched for at least the first affected voice channel.

Abstract: A fast load transient response circuit includes a feedback loop that senses a load transient; a first driver and a second driver responsive to a feedback signal from the feedback loop; and a first pass transistor and a second pass transistor with sources and drains being coupled to each other, and a gate of the first pass transistor being driven by the first driver and a gate of the second pass transistor being driven by the second driver. A width of the channel to length of the channel (W/L) ratio of the first pass transistor is different than that of the second pass transistor such that second pass transistor reacts faster than the first pass transistors to a load transient.

Abstract: A semiconductor die includes a first contact stack including a first die pad having a first pad perimeter, a first via through a dielectric layer to the first die pad having a first via perimeter, and a first UBM pad contacting the first die pad through the first via having a first UBM pad perimeter. A second contact stack includes a second die pad having a second pad perimeter shorter than the first pad perimeter, a second via through the dielectric layer to the second die pad having a second via perimeter shorter than the first via perimeter, and a second UBM pad contacting the second die pad through the second via having a second UBM pad perimeter that is shorter than the first UBM pad perimeter.

Abstract: A probe apparatus may include a plurality of probe pins attached to a probe head portion. Each of the probe pins may be independently movable relative to the probe head portion.

Abstract: Techniques for loosely coupling a Global Navigation Satellite System (“GNSS”) and an Inertial Navigation System (“INS”) integration are disclosed herein. A system includes a GNSS receiver, an INS, and an integration filter coupled to the GNSS receiver and the INS. The GNSS receiver is configured to provide GNSS navigation information comprising GNSS receiver position and/or velocity estimates. The INS is configured to provide INS navigation information based on an inertial sensor output. The integration filter is configured to provide blended position information comprising a blended position estimate and/or a blended velocity estimate by combining the GNSS navigation information and the INS navigation information, and to estimate and compensate at least one of a speed bias and a heading bias of the INS navigation information.

Abstract: Metal contacts with low contact resistances are formed in a group III-N HEMT by forming metal contact openings in the barrier layer of the group III-N HEMT to have depths that correspond to low contact resistances. The metal contact openings are etched in the barrier layer with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer.

Abstract: A method for decoding encoded blocks of pixels from an encoded video bit stream is provided that includes decoding a block vector corresponding to an encoded block of pixels from the encoded bit stream, verifying that the block vector indicates a block of reconstructed pixels in a search area including reconstructed pixels of a largest coding unit (LCU) including the encoded block of pixels and N left neighboring reconstructed LCUs of the LCU, and decoding the encoded block of pixels, wherein the block of reconstructed pixels is used as a predictor for the encoded block of pixels.

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.

Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.