Abstract: In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks.

Abstract: In a bi-directional embodiment, an authorization transponder 114 coupled to the mobile device 128 transmits an interrogating message, which includes a UID 116 associated with the mobile device, to a nearby wireless key 100. The wireless key compares this received UID 116 with the one or more UID's 102 stored on the wireless key, and if a match is detected, sends the wireless key's UID or encrypted variant thereof to the interrogating authorization transponder 114. On receiving the UID from the wireless key 100 and determining that it matches the authorization transponder UID 116, a command is sent from authorization transponder 114 to mobile device 128 enabling some or all operations of mobile device 128.

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract: For determining a power consumption of electrical circuitry, at least one device executes at least a portion of a software application having an effect on a current through the electrical circuitry. A current is generated through a transistor for mirroring the current through the electrical circuitry. In response to a control word, a reference current is generated. In response to executing the portion of the software application, the control word is varied to determine a value thereof that causes the reference current to approximately equal the current through the transistor, in a manner that correlates the effect of the portion of the software application on the current through the electrical circuitry.

Abstract: Amplifier circuits and methods of cancelling the Miller effects in amplifiers are disclosed herein. An embodiment of an amplifier circuit includes an input and an output. An amplifier is connected between the input and the output of the circuit. A voltage source is connected to the output, wherein the voltage source output is one hundred eighty degrees out of phase with the voltage output by the amplifier, and wherein the voltage source cancels gain due to the Miller effect of a Miller capacitance between the input and output.

Abstract: A measurement system includes a current source that is arranged to generate a current pulse to charge a capacitor as a function of an input clock signal. The accumulated charge on the capacitor is converted to a sample (e.g., resultant digital value) by an ADC (analog-to-digital converter). The samples can be aggregated as a distribution in order to estimate the jitter of the input clock signal. Variability of the measurement system can be minimized through calibrating the device-under-test at specific points of PVT (process, voltage, and temperature) conditions. A confidence metric such as a standard of deviation can be derived from the associated samples. The measurement system can be included on a substrate that includes the oscillator that generates the input clock signal.

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Abstract: A flow meter ultrasonically measures fluid velocity in a pipe and ultrasonically transmits fluid flow data along the pipe. An ultrasonic transducer used for fluid velocity measurement may optionally also be used for communication of flow data, and optionally, the ultrasonic frequency for fluid velocity measurement may be the same as the ultrasonic frequency for communication of flow data.

Abstract: Improved preamplifier circuits for converting single-ended input current signals to differential output voltage signals, including first and second transimpedance amplifiers with input transistors operating according to bias currents from a biasing circuit, output transistors and adjustable feedback impedances modified using an automatic gain control circuit, as well as a reference circuit controlling the bias currents according to an on-board reference current and the single-ended input or the differential output voltage signals from the transimpedance amplifiers.

Abstract: Differential voltage mode signal driver circuitry is presented in which a differential current mode amplifier input stage provides a differential signal, and an output stage includes a pair of bipolar transistors receiving the differential signal and being connected in series with a pair of cross-coupled field effect transistors that are coupled to corresponding current sources, where a negative impedance circuit is connected between the field effect transistors to substantially cancel a parasitic capacitance of a driven output circuit.

Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

Abstract: An apparatus for incorporating a metallic foil into a semiconductor package includes a carrier embossed with a multiplicity of cavities. Each of the cavities define a pedestal recessed with the cavities which penetrate only partially through the thickness of the carrier. A metallic foil overlying a pattern with the pedestals in direct contact and help support the metallic foil with the metallic foil pressed into at least some of the cavities. In other embodiments, a gap is between the metallic foil and bottoms of the cavities in a substrate. Integrated circuit dice are attached to the foil. Each die is attached to the foil in a region of the foil overlying a portion of the at least one device area pattern. Bonding wires electrically connect the integrated circuit dice to the foil.

Abstract: In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. When the read address is identical to the write address stored in the pipelined memory, the result of a bit-wise ANDing of data stored in pipelined synchronous data registers and data stored in pipelined synchronous bit-wise registers is presented at the output of the multi-port register file.

Abstract: A method for joining integrated circuit (IC) die. The includes pressing the IC die toward a workpiece so that a protruding bonding feature is inserted into a cavity of a receptacle through an opening. The pressing bends peripheral shelf regions downward into the cavity and towards sidewall portions of the receptacle to form bent peripheral shelf regions. A protruding bonding feature contacts the bent peripheral shelf regions along a contact area. The contact area being at least primarily along the sidewall surfaces of the protruding bonding feature.

Abstract: In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. Which bits of data from a pipelined synchronous data register are written into the multi-port register file is determined by a pipelined synchronous bit-write register. The output of the pipelined synchronous bit-write register selects which inputs of multiplexers contained in registers in the multi-port register file are stored.

Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

Abstract: Systems and methods of dynamic current limit are disclosed herein. A current is sensed a wireless charging circuit, for example. When the current sense reaches a reference current level while a communication is active, the current limit is enabled for the next packet. The current limit signal may be cleared for the next packet.

Abstract: One embodiment includes a preamplifier system. The system includes a reference stage configured to set a magnitude of a clamping voltage for a reference node based on a reference current generated in an adjustable reference current path. The system also includes an output stage comprising an adjustable slew current source that is configured to provide an activation current to the reference node in response to at least one activation signal, the output stage to generate an output current at an output of the output stage with a magnitude that is based on the clamping voltage.

Abstract: A fast load transient response circuit includes a feedback loop that senses a load transient; a first driver and a second driver responsive to a feedback signal from the feedback loop; and a first pass transistor and a second pass transistor with sources and drains being coupled to each other, and a gate of the first pass transistor being driven by the first driver and a gate of the second pass transistor being driven by the second driver. A width of the channel to length of the channel (W/L) ratio of the first pass transistor is different than that of the second pass transistor such that second pass transistor reacts faster than the first pass transistors to a load transient.

Abstract: An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.