Abstract: A method for improving the alignment of the bi-directional scan lines of a resonant mirror imaging system is disclosed. The method includes sensing the position of the mirror and selecting a portion of each scan line, such as the exact middle 50% and the start points of the scan lines in both directions for displaying the image. Determine the specific number of pixels used to modulate the scan lines and the clocking rate at which the pixels are inserted on the light beam so that the pixels completely fill the selected portion of the scan lines. The clock rate is then adjusted to the determined rate.

Abstract: An apparatus for demodulating an Amplitude Shift Keying (ASK) encoded signal is provided. The apparatus comprises a peak detector, a first comparator, a threshold generator, a delay circuit, and a second comparator. The peak detector is configured to detect a peak voltage, and the first comparator is coupled to the peak detector and receives a first threshold voltage. The threshold generator is coupled to the peak detector and is configured to generate a second threshold voltage that is proportional to peak voltage. The delay circuit is coupled to the first comparator, and the second comparator is coupled to the delay circuit and that is coupled to the threshold generator so as to receive the second threshold voltage.

Abstract: An electronic device for a lighting system, comprising a TRIAC dimmer configured to receive a mains supply voltage and provide a phase cut voltage to the electronic device and having a control loop configured to control a duty cycle of a switched voltage converter that receives the rectified input voltage and provides drive current to a light emitting semiconductor device. The control loop has an error amplifier that is coupled to receive a sense voltage that is indicative of a current through the light emitting semiconductor device, the error amplifier is configured to provide a feedback signal to a pulse width modulation logic configured to control the duty cycle of the switched voltage converter to provide a constant drive current to the light emitting semiconductor device in response to the sense voltage, the error amplifier being coupled to receive a reference voltage that is a function of the input voltage.

Abstract: An application specific integrated circuit (ASIC) that includes a digital signal processing (DSP) core and a configurable logic block coupled to the DSP core. The configurable logic block including a plurality of interconnected logic modules to apply a pre-configured logic function to an input. Each of the plurality of logic modules including a controller and a plurality of logic components, the controller of each logic module dynamically reconfigures the connections between the controller's logic module and another logic module.

Abstract: An electronic device, a fiber-optic communication system comprising the electronic device and a method of operating the electronic device are provided. The electronic device comprises a transimpedance-type amplifier having a transimpedance stage comprising an amplifier which is coupled in series with an input node. A feedback resistor is coupled in series between an output node of the amplifier and an inverting input node of the amplifier to provide a virtual ground node which is coupled to the input node, the inverting input node of the amplifier and to the feedback resistor. A current source is coupled to the virtual ground node so as to compensate for an offset current in an input signal which is coupled to the input node of the electronic device. Further, the electronic device comprises a control stage which is configured to control the current source as a function of a current through the feedback transistor.

Abstract: An apparatus for emitting radiation is provided. The apparatus comprises an antenna formed on a substrate, and a high impedance surface (HIS). The HIS has a plurality of cells formed on the substrate that are arranged to form an array that substantially surrounds at least a portion of the antenna. Each cell generally includes a ground plane, first plate, second plate, and an interconnect. The ground plane is formed on the substrate, while the first plate (which is substantially rectangular) is formed over and coupled to the ground plane. The first plate for each cell is also arranged so as to form a first checkered pattern for the array. The second plate (which is substantially rectangular) is formed over and is substantially parallel to the first plate. The first and second plates are also substantially aligned with a central axis that extends generally perpendicular to the first and second plates hand have a interconnect formed therebetween.

Abstract: A method and apparatus for polarity detection. The method includes applying a band-pass filter to an impulse response of a loudspeaker, applying an exponential weighting to the band-pass filtered impulse response, wherein the exponential decay parameter is related to the higher corner frequency of the band-pass filter, finding the maximum peak in a waveform of sampled impulse responses, and detecting the connection polarity of the maximum peak as the polarity of the peak.

Abstract: In an embodiment, a duty cycle correction circuit comprises a first set of inverters connected in series, a first filter, a first feedback circuit and a second feedback circuit. A first inverter in the series is configured to receive a clock signal and a last inverter in the series is configured to provide a first output clock signal. The first filter is configured to generate a first direct current (DC) voltage signal at an output of the first filter. The first feedback circuit is configured to control a rise time of a signal transition at an output terminal of the first inverter to control a duty cycle of the first output clock cycle. The second feedback circuit is configured to control a fall time of the signal transition at the output terminal of the first inverter to control the duty cycle of the first output clock cycle.

Abstract: One embodiment includes a power supply system including a transformer comprising a primary, secondary, and auxiliary winding that are magnetically coupled. The system also includes a switch stage that generates a current through the primary winding in response to activation of a switch based on a control signal that is generated based on a feedback voltage associated with the auxiliary winding. The current can be induced in the secondary winding. The system also includes an output stage coupled to the secondary winding and that generates an output voltage based on the current induced in the secondary winding. The system further includes a feedback stage coupled to the auxiliary winding and comprising a discriminator configured to determine a zero-current condition associated with the current induced in the auxiliary winding based on monitoring a change in slope of the feedback voltage and to measure the feedback voltage during the zero-current condition.

Abstract: An embodiment of the invention includes first and second Ternary Content Addressable Memories (TCAMs), a first vector, and TCAM match-merge unit. Each of the TCAMs includes a plurality of words, stores TCAM match entries and outputs a TCAM match signal for each word in the plurality of words. The first vector includes first TCAM group enable register bits. An enabling value on the first TCAM register bit indicates that the first TCAM match signal and the neighboring first TCAM match are in the same TCAM group. The TCAM match-merge unit receives the first TCAM match signal from each of the words and the first vector and outputs a first TCAM group match signal for each of the words. The TCAM match-merge unit outputs a match indication when any of the TCAM match signals indicate a match and outputs a mismatch when none of the TCAM match signals match.

Abstract: An apparatus having an X-ray sensor assembly with X-ray blocking pixels divided by X-ray transmitting gaps with the X-ray blocking pixels casting an X-ray blocking shadow; and a die containing signal processing electronics, with the signal processing electronics positioned substantially entirely within the X-ray blocking shadow. A method for detecting the alignment between the X-ray sensor assembly and the die is disclosed. Also disclosed is an X-ray computed tomography machine having a printed circuit board (“PCB”), a die embedded in the PCB, and a signal source wherein signals are routed to and from the die by traces on at least one of the surfaces of the PCB.

Abstract: A power supervisor circuit is provided. The circuit includes a first sample circuit that periodically samples a first reference voltage derived from a high output rail of a voltage source and generates a first sampled output voltage. The circuit includes second sample circuit that periodically samples a second reference voltage associated with a low output rail of the voltage source and generates a second sampled output voltage. A voltage supervisor in the circuit generates a trip point signal when a combination of the first and second sampled output voltage crosses a predetermined threshold indicating that the voltage source output voltage has fallen below a desired output voltage.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: A method is provided. An initial bit sequence is received by a receiver. A local oscillator is locked initially to a local reference and subsequently to the received signal using the initial bit sequence, and automatic gain control (AGC) is performed once the local oscillator is locked to the local reference. A Costas loop is then activated so as to achieve carrier frequency offset (CFO) lock, and sign inversion is detected. The receiver then synchronized with an end-of-training pattern.

Abstract: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.

Abstract: In a method and apparatus for determining the level of dynamic force required to cause damage to an electronic device, the electronic device may be placed beneath a ram assembly of a dynamic impact testing device. Thereafter, the ram assembly may be used to impact the electronic device to determine a threshold level of dynamic force that will cause damage to the electronic device. The ram assembly may then be used to impact a load cell with the threshold level of dynamic force so that the load cell generates a data output.

Abstract: In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks.

Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: A method of ultrasound receive beamforming includes receiving a first plurality of sensing signals from target tissue, forming a first plurality of digital sensing signals, and data processing the digital sensing signals along a first plurality of data paths to form a first plurality of delayed and apodized digital sensing signals. Data path combining generates data combinations of the delayed and apodized digital sensing signals to include two or more of the delayed and apodized digital sensing signals that originate from different ones of the transducer elements. The data combinations are interpolation filtered using a plurality of interpolation filters to form a second plurality of delayed and apodized digital sensing signals, which are then summed to form an ultrasound receive beamformed signal. The interpolation filters can be interpolation filters in a single shared filter bank, with each interpolation filter providing a different fractional delay.