Abstract: Circuits, and methods for reducing standby leakage power in Integrated Circuit (ICs) are disclosed. In an embodiment, an IC includes a core circuit, a first switch and a second switch, where the first switch is coupled between a power terminal of the core circuit and a power supply and the second switch is coupled between a ground terminal of the core circuit and a ground supply. The first switch and the second switch are configured to power ON and OFF the core circuit. The IC includes a first feedback circuit configured to control ON and OFF states of the first switch based on voltage at the power terminal, and a second feedback circuit configured to control ON and OFF states of the second switch based on voltage at the ground terminal of the core circuit during the standby mode for maintaining the logic state of the core circuit.

Abstract: A method for communicating signals in an ultra high bandwidth system that compensates for carrier frequency offset is provided. A baseband transmit signal having a plurality of data bits is generated. The baseband transmit signal is upconverted to a radio frequency (RF) transmit signal using a first local oscillator signal having a first carrier frequency. An offset cancellation for the offset between the first carrier frequency and a second carrier frequency for a second local oscillator signal that is used to downconvert an RF receive signal is calculated. The offset cancellation is applied to a plurality of phase rotators, and the RF transmit signal is transmitted over a phased array.

Abstract: A password element is generated for a station running an Elliptic Curve Cryptography (ECC) or a Finite Field Cryptography (FFC) group based password authenticated protocol. A password element is multiplied by a cofactor to generate a modified password element for the ECC group. The station verifies that the modified password element is not equal to a point at infinity for the ECC group. A password element is generated by exponentiating a password value to a power t, where t=(p?1)/r, p and r are primes, and r has a bit length of at least 160 bits for the FFC group. A commit-element parameter is generated using a temporary secret value and the ECC modified password element or the FFC password element, and is then transmitted to another station in a commit message. The receiving station checks if the received commit-element parameter has desired properties before continuing with the protocol.

Abstract: The noise reduction filter is intensity adaptive and incorporates directional variances of input images.

Abstract: Embodiments of the invention provide a method of de-rate matching without NULL bits skipping. Date is received without NULLs and inputted into a LLR combining block. The history data without NULLs is buffered. Log-likelihood ratio (LLR) combining is called before de-rate matching. The output of LLR combining is de-interleaved. The reading pointer is offset to forge NULLs. Finally, de-interleaving output without NULLs is sent to a turbo decoder.

Abstract: A power supply module (400) comprising a metal leadframe with a pad (401) and a first metal clip (440) including a plate (440a), an extension (440b) and a ridge (440c); the plate and extension are spaced from the leadframe pad, and the ridge connected to an input supply. A synchronous Buck converter is in the space between the clip plate and the leadframe pad, the converter including a control FET die (410) soldered onto a sync FET die (420), the clip plate soldered to the control die having an input inductance (462), and the sync die soldered to the leadframe pad having an output capacitance. A capacitor (480a, 480b) integrated into the space between the clip extension and the leadframe pad, the clip extension soldered to the capacitor having a desired integrated inductance (463) operable to channel electrical energy from the switch node to ground.

Abstract: According to one embodiment of the present invention a digital micro-mirror device is taught that includes a pixel occupying an area of the device and a hinge coupled to the pixel and positioned such that at least a portion of the hinge falls outside the area of the pixel.

Abstract: A process flow exposing and cleaning contact surfaces employing a liquid cleaning agent such as flux to penetrate the interface between the glassy coats and the surface of metal and to delaminate the coats from the metal, and then, at elevated temperatures, to use the agent's vapor pressure to break up the glassy coats into smaller pieces. The glassy coats are prevented by their low density to penetrate into the molten solder. Finally, at ambient temperature, the floating filler debris is water-washed and rinsed away. Cleaning agents include low-viscosity liquids (oils) and flux, which do not decompose at elevated temperatures and are mixed with components operable to provide, at the elevated temperatures, the fumes for sufficient vapor pressure to break up and dislodge the coats from the metal contacts.

Abstract: A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: In accordance with the teachings of the present invention, a system and method for increasing the bit-depth of a video display system using a pulse lamp are provided. In one embodiment, the method includes illuminating a digital micro-mirror device with a light source having a variable power supply, receiving a signal indicating the light output provided to the digital micro-mirror device by the light source should be reduced to a target level during a predetermined time period, reducing a power supplied to the light source by the variable power supply in response to the signal such that the light output of the light source is reduced to about a target level during the predetermined time period, displaying a least significant bit on the digital micro-mirror device during the predetermined time period, and decreasing a speed of a master clock controlling the digital micro-mirror device in response to the light output of the light source deviating below the target level during the predetermined time period.

Abstract: A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to the top electrode of the capacitor by etching small capacitor vias during a bond pad via etch process, followed by depositing and patterning bond pad metal in the capacitor vias to connect the top electrode to other circuit elements in the IC. The top electrode thickness is increased to accommodate the bond pad via etch process.

Abstract: A screening method for testing solid-state memories for the effects of long-term shift and random telegraph noise (RTN). In the context of static random access memories (SRAMs), each memory cell in the array is functionally tested with a bias voltage (e.g., the cell power supply voltage) at a severe first guardband sufficient to account for worst case long-term shift and RTN effects. Cells failing the first guardband are then repeatedly tested with the bias voltage at a second guardband, less severe than the first guardband; if the tested cells pass this second guardband, the suspect cells are considered to not be vulnerable to RTN effects. Over-screening due to an unduly severe guardband is avoided, while still screening vulnerable memories from the population.

Abstract: A method and system for sub-circuit pattern recognition in integrated circuit design is disclosed. In one embodiment, a method for recognizing a pattern circuit in a target circuit, includes encoding the pattern circuit and the target circuit by processing a first netlist of the pattern circuit and a second netlist of the target circuit, generating a cross-linked data structure based on attributes and connectivity information of at least two devices and at least one net from the first netlist, and identifying an instance of the pattern circuit in the target circuit based on an associative mapping between the pattern circuit and a sub-circuit of the target circuit using a device integer array and a net integer array. Each of the first netlist and the second netlist is based on the at least two devices and the at least one net connecting the at least two devices.

Abstract: A dynamic gain equalizer-monitor (DGEM) includes a light modulator operable to modulate one or more component wavelengths of an input optical signal. The DGEM also includes a grating operable to receive one or more modulated component wavelengths from the light modulator. The grating is also operable to combine a first portion of each of the one or more modulated component wavelengths and transmit that first portion into an output optical signal. The DGEM may also include a detector array operable to receive, from the grating, a second portion of modulated component wavelengths that are separated from the first portion by the grating. The detector array is operable to generate an electrical signal proportional to an optical characteristic associated with each of the modulated component wavelengths of the second portion.

Abstract: A method for manufacturing a mirror device is presented. The method includes forming a mirror from a first substrate and forming a hinge/support structure from a second substrate. The hinge/support structure is formed with a recessed region and a torsional hinge region. The mirror is attached to the hinge/support structure at the recessed region. Further, a driver system is employed to cause the mirror to pivot about the torsional hinge region.

Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Abstract: A method for calibrating a reflection compensator is provided. A delay is initially set to a predetermined minimum, and an input pulse is transmitted across a transmission line. A compensation current is then applied after the delay. The reflection from the transmission line is digitized to generate a measurement, and a determination is made as to whether the compensation current substantially compensates for the reflection. If the compensation current does not substantially compensate for the reflection, then the delay is adjusted, and the process is repeated until the compensation current substantially compensates for the reflection.

Abstract: Navigation system receiver, and test circuits and methods for determining drift profile of a receiver clock in the navigation system receiver are disclosed. In an embodiment, the navigation system receiver includes a clock source configured to generate a receiver clock for the navigation system receiver and a test circuit. The test circuit is configured to facilitate determination of a drift profile associated with the receiver clock based on detection and tracking of a test signal received by the test circuit, where the test signal comprises at least one continuous wave (CW) signal.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.