Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.

Abstract: An apparatus includes an amplifier configured to compare a feedback input, corresponding to a voltage of an output voltage node, with respect to a reference input and to provide a control output to control the output voltage node based on a difference between the feedback input and the reference input. At least two source circuits are coupled with the output voltage node. Each of the source circuits are configured to provide respective voltage sources to supply electrical power to the output voltage node.

Abstract: A sample and hold circuit with long hold time. A sample and hold circuit includes an amplifier, a capacitor, a switch, and a sampling network. The capacitor includes a first terminal coupled to an inverting input of the amplifier. The switch includes a first terminal that is coupled to an output of the amplifier, and a second terminal that is coupled to the inverting input of the amplifier. The sampling network is coupled to a non-inverting input of the amplifier.

Abstract: Hysteretic control for power converters. In an example arrangement, an apparatus includes a converter for converting an input voltage to an output voltage including a transformer; at least one primary side driver switch coupled to supply current from an input voltage terminal to the primary side of the transformer; at least one inductor coupled between the secondary side of the transformer and the output voltage terminal; at least one secondary side switch coupled between the inductor and a ground potential; and a hysteretic controller coupled to supply a first on-time signal to the at least one primary side switch and a second on-time signal to the at least one secondary side switch, the hysteretic controller configured for sensing the output voltage and having at least one current input coupled for sensing current flowing in the inductor and generating primary side driver switch on-time pulses to control the output voltage.

Abstract: A switch-node rising edge detection circuit is provided for a switched-mode DC/DC boost converter. A high-side gate-driver couples a gate of the high-side NMOS power transistor to either a first terminal of a bootstrap capacitor or the switch-node. The detection circuit includes an AND gate that receives an activation signal on a first input and provides a switching signal to the high-side gate-driver. A PMOS transistor is coupled in series with an inverter between the first terminal of the bootstrap capacitor and a second input of the AND gate. The inverter receives supply voltages from the first terminal of the bootstrap capacitor and the switch-node. The gate of the PMOS transistor receives the activation signal. An NMOS transistor is coupled between an output voltage and a node between the PMOS transistor and the inverter. A gate of the NMOS transistor is coupled to the bootstrap capacitor's first terminal.

Abstract: A power factor correction controller zero current detection circuit includes a differentiator circuit, a comparator, a first qualification timer circuit, an idle ringing detector circuit, a second qualification timer circuit, and a flip-flop. The comparator is coupled to the differentiator circuit. The first qualification timer circuit includes an input coupled to an output of the comparator. The idle ringing detector circuit includes a first input coupled to the output of the comparator, and a second input coupled to an output of the first qualification timer circuit. The second qualification timer circuit includes a first input coupled to the output of the first qualification timer circuit, and a second input coupled an output of the idle ringing detector circuit. The flip-flop includes a first input coupled to the output of the comparator, and a second input coupled to an output of the second qualification timer circuit.

Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: A rear-stitched view panorama (RSVP) system is provided that includes at least one processor and a memory storing software instructions that, when executed by the least one processor, cause the RSVP system to compute a disparity map for a left center rear image and a right center rear image captured by a stereo camera mounted on a rear of a vehicle, transform a right rear image, a left rear image, a reference center rear image, and the disparity map to a virtual world view, the right rear image and left rear image captured by respective right and left cameras mounted on the vehicle, compute an optimal left seam and an optimal right seam based on the transformed disparity map, and stitch the transformed images based on respective optimal seams to generate a panorama.

Abstract: An audio circuit includes an amplifier, a voltage sensor, a current sensor, and an excursion control circuit. The voltage sensor is coupled to an output of the amplifier. The current sensor is coupled to the output of the amplifier. The excursion control circuit is coupled to the amplifier, the voltage sensor, and the current sensor. The excursion control circuit includes back electro-magnetic force (EMF) measurement, a back-EMF model, and excursion protection. The back-EMF measurement is to measure back electro-magnetic force of a speaker based on voltage measurements received from the voltage sensor and current measurements received from the current sensor. The back-EMF model is updated based on measurements of the back-EMF and is converted to an excursion model. The excursion protection is to limit amplitude of audio signal provided to the amplifier based on the excursion model of the speaker and amplitude of an audio input signal.

Abstract: In described examples, a radio frequency (RF) resonator including a cavity and a tuning component, where the cavity includes a resonance property that can be changed in response to the tuning component. A transmitter generates an RF signal at each of a set of determined frequencies for transmitting individually within the cavity. A receiver receives the RF signal transmitted individually at each of the determined frequencies and determines a respective amplitude for each of the determined frequencies.

Abstract: Methods and apparatus for parsing friendly and error resilient merge flag coding in video coding are provided. In some methods, in contrast to merging candidate list size dependent coding of the merge flag in the prior art, a merge flag is always encoded in the encoded bit stream for each inter-predicted prediction unit (PU) that is not encoded using skip mode. In some methods, in contrast to the prior art that allowed the merging candidate list to be empty, one or more zero motion vector merging candidates formatted according to the prediction type of the slice containing a PU are added to the merging candidate list if needed to ensure that the list is not empty and/or to ensure that the list contains a maximum number of merging candidates.

Abstract: An analog-to-digital converter has a logic gate for generating an output signal having a delay corresponding to a delay between input signals. The logic gate includes inputs for receiving the input signals, and an output for outputting the output signal. A delay comparator generates a digital signal representative of the order of the input signals, and generates a delay signal having a delay corresponding to the delay between the input signals. The delay comparator has inputs for receiving the input signals, a digital output for outputting the digital signal, and a delay output for outputting the delay signal. A delay-based analog-to-digital converter, with a front stage and successive residual stages, is also disclosed. A delay comparator having merged comparator, sign-out, and delay-out circuits, and which may be operated within one of successive stages, without a clock, is also disclosed.

Abstract: An analog-to-digital converter has first and second comparators and an interpolation comparator. The first comparator receives an input signal and a comparison signal, and generates an output as a function of the input signal and the comparison signal. The second comparator receives the input signal and a second comparison signal (different from the first comparison signal), and generates a second output as a function of the input signal and the second comparison signal. The interpolation comparator, operatively connected to the first and second comparators, receives the first and second outputs, and generates a third output based on relative timing of the first and second outputs.

Abstract: A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a photo-imageable polyimide or epoxy material to form the adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame blank and using a photo-imageable polyimide or epoxy material to form the adhesion layer.

Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.

Abstract: In described examples, in response to a voltage at an external power terminal falling below a safe limit: a charge pump is operated at a first frequency to produce a voltage at a charge pump node; and a first controlled current is coupled from the charge pump node to a control terminal of a power switch transistor. The power switch transistor has a conduction path coupled between the external power terminal and an internal power terminal at which an internal power source is connected. In response to the voltage at the external power terminal reaching a selected level: the charge pump is operated at a second frequency, lower than the first frequency; and a second controlled current, lower than the first controlled current, is coupled from the charge pump node to the control terminal of the power switch transistor.

Abstract: A method of bondwire integrity testing a packaged IC includes forcing a pin current or pin voltage level sufficient to forward bias a parasitic diode at a plurality of pins relative to a selected reference pin. The pins are connected to bond pads (BPs) on the IC by a bondwire. The bond pads coupled to a diffusion of a first type that forms the parasitic diode (D) with a region doped the second type coupled to a bondpad wirebonded to the reference pin. The resulting pin voltages or pin currents at measured, and present pin-pin relationships are determined. The present pin-pin relationships are compared to stored pin-pin relationship data for a device design of the IC. Results from the comparing are used to determine whether any present pin-pin relationships are significantly different as compared to the stored pin-pin relationships to identify a bondwire problem for at least one pin.

Abstract: In an integrated circuit, a metal-insulator-metal (MIM) diode includes: a first metallization structure level having a first metal layer; a first dielectric layer over the first metal layer; a metal contact or via on the first metal layer and extending through a portion of the first dielectric layer; and a second metallization structure level having a second metal layer; and a second dielectric layer over the second metal layer. The diode has a first electrode on the metal contact or via, a multilayer dielectric structure on the first electrode, and a second electrode between the multilayer dielectric structure and the second metal layer.

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.