Abstract: A device and method of forming the device that includes a first substrate having a cavity on a bottom surface of the first substrate and MEMS components formed on the first substrate and in the cavity; a second substrate having an upper surface; a first metal bond that extends around a perimeter of the cavity and forming a first connection between the bottom surface of first substrate and the upper surface of the second substrate; a second metal bond that extends around a perimeter of the first metal bond and spaced from the first metal bond, the second metal bond forming a second connection between the bottom surface of the first substrate and the upper surface of the second substrate; where the MEMS components are hermetically sealed between the first and second substrates. A getter agent can be between the first and second metal bonds.

Abstract: A packaged electronic device includes a die pad directly connected to a first set of conductive leads of a leadframe structure, a semiconductor die attached to the conductive die pad, a conductive support structure directly connected to a second set of conductive leads, and spaced apart from all other conductive structures of the leadframe structure. A magnetic assembly is attached to the conductive support structure, and a molded package structure that encloses the conductive die pad, the conductive support structure, the semiconductor die, the magnetic assembly and portions of the conductive leads, the molded package structure including a top side, and an opposite bottom side, wherein the lamination structure is centered between the top and bottom sides.

Abstract: In described examples, a Hall effect sensor includes a primary Hall effect sensor element and an auxiliary Hall effect sensor element. A known magnetic field is applied to the auxiliary Hall effect sensor to produce an auxiliary Hall voltage used in a feedback loop to control the bias current of the auxiliary Hall effect sensor to maintain the auxiliary Hall voltage approximately constant over a range of temperature and other factors. A bias current for the primary Hall effect sensor is controlled to track the bias current of the auxiliary Hall effect sensor to maintain the sensitivity of the primary Hall effect sensor approximately constant over the same range of temperature and other factors.

Abstract: An optical distance measuring system includes a transmitter and a receiver. The transmitter is configured to generate a first optical waveform and direct the first optical waveform toward a first scan point within a field of view (FOV). The receiver is configured to receive the first optical waveform reflected off a first object within the FOV, direct the first optical waveform reflected off the first object to a first photodiode group of an array of photodiode elements, and determine a distance to the first object based on a time of flight of the first optical waveform from the transmitter to the first object and back to the receiver.

Abstract: A gate driver circuit includes a comparator and a gate driver. The comparator is configured to detect a short circuit in a first power field effect transistor (FET). The gate driver is configured to drive a gate of the first power FET by generating a first signal at a first drive current. In response to the comparator detecting a short circuit in the first power FET, the gate driver is further configured to pulse the first signal at a first pulldown current. After the pulse has ended, the gate driver is further configured to drive the gate of the first power FET at a first hold current. The first hold current is less than the first pulldown current.

Abstract: Channel switchover power multiplexer circuits, and methods of operating the same are disclosed. An example power multiplexer a first transistor coupled to a first input, a second transistor coupled to the first transistor to couple a first voltage at the first input to an output, a third transistor coupled to a second input, a fourth transistor coupled to the third transistor to couple a second voltage at the second input to the output, a diode amplifier to provide a third voltage to a gate of the first transistor to block a reverse current, and a soft-start amplifier to provide a fourth voltage to a gate of the fourth transistor to turn on (with adjustable VOUT ramp rate) the fourth transistor with a constant ramp rate.

Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.

Abstract: A communication system and method includes a receiver for receiving a communication signal coupled through a physical medium in accordance with a protocol. An interface formed in a single substrate receives from the receiver an indication of the signal strength of the received communication signal. The interface also decodes the information contained in the received communication signal. For example, the interface sends the information decoded from the received communication signal to a first application for consuming the decoded information. The interface also sends the indication of the signal strength of the received communication signal to a second application for generating a quality determination of the physical medium in response to the indication of the signal strength of the received communication signal.

Abstract: A level translator translates signals between first and second voltage domains. An output buffer thereof includes a plurality of PFETs coupled in parallel between a second domain's output supply voltage and an output signal and a plurality of NFETs coupled in parallel between the output signal and the ground rail. Each gate of the plurality of PFETs is coupled to a respective first resistor; the first resistors are coupled in series and receive a first gate control signal. Each gate of the plurality of NFETs is coupled to a respective second resistor; the second resistors are coupled in series and receive a second gate control signal. A first booster NFET is coupled between the output supply voltage and the output signal and a second booster NFET is coupled between the output signal and the ground rail. The booster NFETs receive control signals that operate in the first voltage domain.

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

Abstract: A power combining technique includes receiving a first voltage at a first input and a second voltage at a second input. The power combining technique further includes combining, with at least two power converters, power received from the first and second inputs into a single power rail. A power balancing technique further includes controlling the at least two power converters such that a first one of the power converters outputs an amount of current to the single power rail that is proportional to and/or equal to the amount of current output by another of the power converters.

Abstract: Some aspects of the disclosure provide for a circuit. In an example, the circuit includes an amplifier, a first transistor network, a second transistor network, a first resistor, a second resistor, and a third resistor. The amplifier has first and second inputs and first, second, third, and fourth outputs. The first transistor network is coupled to the first output of the amplifier and the second output of the amplifier. The second transistor network is coupled to the third output of the amplifier and the fourth output of the amplifier. The first resistor is coupled between the first transistor network and the second transistor network. The second resistor is coupled between the first transistor network and the first input of the amplifier. The third resistor is coupled between the second transistor network and the second input of the amplifier.

Abstract: A current-sense ratio calibration system includes a power field effect transistor (FET) integrated circuit (IC) that includes a regulator FET to regulate current through a power path and a sense FET to provide a sense current to a sense path. The regulator FET and sense FET have an intended current-sense ratio. The system calibrates the current-sense ratio by applying proportioned stimulus signals to the power and sense paths, the proportion being the intended current-sense ratio. The calibration circuitry compares a measurement of a sense path circuit parameter made during the stimulus application to a measurement of the parameter made not during the stimulus application to derive an error term used to calibrate for any sources of error in the current-sense ratio.

Abstract: A control system for cleaning and monitoring a sensor assembly disposed externally on a vehicle is provided and includes a contaminant detection/identification sub-system that measures a resonant frequency of the sensor assembly to detect contaminants disposed on an exposed surface of the sensor assembly. A cleaning sub-system is provided and includes cleaning modes that expel the contaminants from the exposed surface of the sensor assembly. A temperature monitoring device monitors a temperature of an actuator disposed in the sensor assembly and a fault detection device detects faults in the sensor assembly.

Abstract: A method of regenerative braking includes providing an electric motor including at least one stator and a rotor, a speed of the rotor, a motor controller that regulates a current level in the stator winding, a power inverter which controls an energy flow to the stator terminal, and an energy storage system (ESS) which exchanges energy with the motor. A battery management circuit is between the power inverter and the ESS, and a processor has an associated memory storing a regenerative braking (RB) algorithm. The RB algorithm during braking causes the motor controller to execute determining an RB torque value from the rotor speed that maximizes regenerative braking current, and the power inverter is used to redirect the RB current to maximize a power transfer from the motor to the ESS.

Abstract: Methods and apparatus to determine nearfield localization using phase and received signal strength indication (RSSI) diversity are disclosed. An example method includes determining a first strength of an electric field and a second strength of a magnetic field, the electric field and the magnetic field associated with an electromagnetic signal sent from a transmitter; determining a difference between the first strength and the second strength; and determining a transmitter distance based on the difference between the first strength and the second strength.

Abstract: A microelectronic device, in a fan-out fan-in chip scale package, has a die and an encapsulation material at least partially surrounding the die. Fan-out connections from the die extend through the encapsulation material and terminate adjacent to the die. The fan-out connections include wire bonds, and are free of photolithographically-defined structures. Fan-in/out traces connect the fan-out connections to bump bond pads. The die and at least a portion of the bump bond pads partially overlap each other. The microelectronic device is formed by mounting the die on a carrier, and forming the fan-out connections, including the wire bonds, without using a photolithographic process. The die and the fan-out connections are covered with an encapsulation material, and the carrier is subsequently removed, exposing the fan-out connections. The fan-in/out traces are formed so as to connect to the exposed portions of the fan-out connections, and extend to the bump bond pads.

Abstract: A microelectronic device, in a leaded/leadless chip scale package, has a die and intermediate pads located adjacent to the die. The intermediate pads are free of photolithographically-defined structures. Wire bonds connect the die to the intermediate pads. An encapsulation material at least partially surrounds the die and the wire bonds, and contacts the intermediate pads. Package leads, located outside of the encapsulation material, are attached to the intermediate pads. The microelectronic device is formed by mounting the die on a carrier, and forming the intermediate pads on the carrier without using a photolithographic process. Wire bonds are formed between the die and the intermediate pads. The die, the wire bonds, and the intermediate pads are covered with an encapsulation material, and the carrier is subsequently removed, exposing the intermediate pads. The package leads are attached to the intermediate pads.

Abstract: An apparatus includes a clip mounted to a base that pivots about a first pivot axis between a first position and a second position. An abutment surface of the clip is spaced from a path of a carrier structure when the clip is in the first position. The abutment surface engages the carrier structure to secure the carrier structure and a device to the apparatus when the clip is in the second clip position. A cam includes a first surface that pivots the clip to the first clip position when the cam is in the first cam position. The cam includes a second surface that extends into an opening of the base when the cam is in a first position to allow a stop plate pin to engage the cam to rotate the cam from the first position to a second position when a stop plate is installed.

Abstract: A microelectronic device, in a fan-out chip scale package, has a die and an encapsulation material at least partially surrounding the die. The microelectronic device includes bump bond pads adjacent to the die that are exposed by the encapsulation material, the bump bond pads being free of photolithographically-defined structures. Wire bonds connect the die to the bump bond pads. The microelectronic device is formed by mounting the die on a carrier, and forming the bump bond pads adjacent to the die without using a photolithographic process. Wire bonds are formed between the die and the bump bond pads. The die, the wire bonds, and the bump bond pads are covered with an encapsulation material, and the carrier is subsequently removed, exposing the bump bond pads.