Abstract: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

Abstract: An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.

Abstract: A method for adaptive loop filtering of a reconstructed picture in a video encoder is provided that includes determining whether or not sample adaptive offset (SAO) filtering is applied to the reconstructed picture, and using adaptive loop filtering with no offset for the reconstructed picture when the SAO filtering is determined to be applied to the reconstructed picture.

Abstract: A Convolutional Neural Network (CNN) based-signal processing includes receiving of an encrypted output from a first layer of a multi-layer CNN data. The received encrypted output is subsequently decrypted to form a decrypted input to a second layer of the multi-layer CNN data. A convolution of the decrypted input with a corresponding decrypted weight may generate a second layer output, which may be encrypted and used as an encrypted input to a third layer of the multi-layer CNN data.

Abstract: A system and method for monitoring energy use in an electronic device. In one embodiment, an energy monitoring system includes a processor and an energy monitor module. The energy monitor module includes instructions that when executed cause the processor to receive values of measured parameters of a pulse signal that controls the switching of energy to an energy storage device in a switch mode power supply that provides power to an electronic device. The instructions also cause the processor to determine, based on the values of measured parameters, attributes of operation of the electronic device powered by the energy source during an interval corresponding to the measured parameters. The instructions further cause the processor to generate, based on the attributes of operation, a control signal that causes the electronic device to change the loading of the power supply by the electronic device.

Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract: In a described example, an integrated circuit includes an input coupled to receive a plurality of beacon frames, the beacon frames include an indication of data transmissions available for a device that includes the integrated circuit. The integrated circuit also includes a controller configured to compare the plurality of beacon frames to determine a plurality of bytes prior to the indication of data transmission available that is present in each of the plurality of beacon frames and is configured to provide a signal indicating a low power mode in which the device does not receive transmissions and to provide a signal indicating a wake mode at a selected time before transmission of the plurality of bytes in a subsequent beacon transmission.

Abstract: An analog signal-to-pulse width modulation (PWM) converter includes a ramp generator generating a ramp signal and a comparator circuit comparing the ramp signal to a first voltage, a second voltage, and an analog input signal. A duty cycle calculation circuit generates a first control signal to the ramp generator to generate the ramp signal. Based on signals from the comparator circuit, the duty cycle calculation circuit calculates the ratio of the time it takes for the ramp signal to exceed the analog input signal from when the ramp signal exceeds the first voltage to the time it takes for the ramp signal to exceed the second voltage from when the ramp signal exceeds the first voltage. A PWM signal generator generates a PWM output signal based on the ratio calculated by the duty cycle calculation circuit.

Abstract: A integrated circuit device includes digital-to-analog converter (DAC) circuitry including a resistor DAC that includes a resistor-two-resistor DAC configured to receive a first sub-word that includes a most significant bit (MSB) of a digital input signal and to output an analog output signal representative of the first sub-word, a resistor ladder configured to receive the analog output signal and a second sub-word that includes an intermediate significant bit (ISB) of the digital input signal and to generate an analog interpolated signal. The resistor ladder includes a plurality of resistor elements connected in series with one another to define a plurality of tap nodes, wherein a respective tap node is arranged between every two adjacent ones of the resistor elements, and a switching circuit having plurality of switches, wherein each switch is configured to selectively connect a respective one of the tap nodes to an output of the resistor ladder to generate the analog interpolated signal.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to enable Digital Satellite Equipment Control (DiSEqC) communication between an antenna and a processor. An example apparatus includes a receiver to be coupled to an antenna by a cable and configured to bidirectionally communicate with the antenna via a communication signal having a periodic waveform, wherein the receiver further includes a low dropout regulator (LDO) pass transistor to be coupled to the cable and configured to generate a current signal based on the periodic waveform of the communication signal, a current envelope detector circuit coupled to the LDO pass transistor configured to generate a voltage signal based on the current signal, and a processor. The processor is coupled to the current envelope detector circuit and configured to process the voltage signal generated by the current envelope detector.

Abstract: A method for adaptive loop filtering is provided that includes determining a coefficient value for each coefficient position of an adaptive loop filter, applying the adaptive loop filter to at least a portion of a reconstructed picture using the coefficient values, and entropy encoding coefficient values into a compressed bit stream using predetermined short binary codes, wherein the short binary code used depends on the coefficient position of the coefficient value.

Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

Abstract: A test assembly includes multiple circuit boards. Each board includes multiple pairs of contacts configurable to address the respective circuit board, an instrument, first and second headers at opposing edges of the respective board. Each pin of a first header electrically connects through the board to a corresponding pin of a second header. Each board includes first and second input/output (I/O) terminals at opposing edges of the respective board, the first I/O terminal electrically connects through the board to the second I/O terminal. A relay on the board permits the board's instrument to be activated. Each of the circuit boards mechanically and electrically connects to another circuit board through a jumper cable connecting the first header of one circuit board to the second header of another circuit board and through a conductive member electrically connecting the first I/O terminal of one board to the second I/O terminal of another board.

Abstract: A battery charger can include a charger controller configured to determine a total charge time that characterizes a time needed to charge a battery, the total charge time being based on a received state of charge (SOC) of the battery that characterizes a present SOC of the battery. The charger controller can also be configured to determine a charging start time for the battery based on a predetermined full charge time and the total charge time.

Abstract: A computer vision system is provided that includes a camera capture component configured to capture an image from a camera, a memory, and an image compression decompression engine (ICDE) coupled to the memory and configured to receive each line of the image, and compress each line to generate a compressed bit stream. To compress a line, the ICDE is configured to divide the line into compression units, and compress each compression unit, wherein to compress a compression unit, the ICDE is configured to perform delta prediction on the compression unit to generate a delta predicted compression unit, compress the delta predicted compression unit using exponential Golomb coding to generate a compressed delta predicted compression unit, and add the compressed delta predicted compression unit to the compressed bit stream.

Abstract: An integrated fluxgate device has a magnetic core disposed over a semiconductor substrate. A first winding is disposed in a first metallization level above and a second metallization level below the magnetic core, and is configured to generate a first magnetic field in the magnetic core. A second winding is disposed in the first and second metallization levels and is configured to generate a second magnetic field in the magnetic core. A third winding is disposed in the first and second metallization levels and is configured to sense a magnetic field in the magnetic core that is the net of the first and second magnetic fields.

Abstract: An electronic device includes first leads along a first side, second leads along a second side, first and second dies, and a magnetic assembly with a multilevel lamination structure with first and second windings and a conductive guard trace. The lamination structure includes the first winding in a first level, and the second winding in a different level. The guard trace is between the first patterned conductive feature and the second side of the package structure. A first set of electrical connections couple the first die, the first winding, and one of the first conductive leads in a first circuit, and a second set of electrical connections couple the second die, the second winding, the guard trace and one of the second conductive leads in an isolated second circuit.

Abstract: A method includes electroplate depositing a first metal layer to a first thickness on a metal seed layer, rinsing the first metal layer with deionized water, and after the first rinse process, drying the wafer. The method also includes performing one or more additional electroplating processes that respectively deposit an additional metal layer to a second thickness over the first metal layer, performing an additional rinse process that rinses the additional metal layer with deionized water, and performing an additional drying processes that dries the wafer.

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.