Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

Abstract: The disclosure provides a radar apparatus for estimating a position and a velocity of the plurality of obstacles. The radar apparatus includes a local oscillator that generates a first signal. A first transmit unit receives the first signal from the local oscillator and generates a first transmit signal. A frequency shifter receives the first signal from the local oscillator and generates a second signal. A second transmit unit receives the second signal and generates a second transmit signal. The frequency shifter provides a frequency offset to the first signal based on a routing delay mismatch to generate the second signal such that the first transmit signal is phase coherent with the second transmit signal.

Abstract: A program is executed on a processor to produce execution events. The execution events are traced using a first trace mode during a first portion of the program execution, wherein a portion of trace information for the execution events is omitted from a trace report while tracing in the first trace mode. The mode of tracing is dynamically changed to a second trace mode in response to an event trigger, such that all execution events that occur during the change of mode are captured. Execution events are traced during a second portion of the program execution using the second trace mode, wherein additional trace information for the execution events is included in the trace report while tracing in the second trace mode. The trace mode may be dynamically switched between the two trace modes during execution of the program.

Abstract: In described examples of a micromechanical system (MEMS), a rigid cantilevered platform is formed on a base substrate. The cantilevered platform is anchored to the base substrate by only a single anchor point. A MEMS resonator is formed on the cantilevered platform.

Abstract: A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.

Abstract: A bandgap voltage circuit with a first circuit to generate an output voltage as a sum of a first voltage with an amplitude that is proportional to absolute temperature, and a first feedback voltage with an amplitude that is complementary to absolute temperature, a second circuit to generate a voltage having an amplitude that is complementary to absolute temperature, a scaling circuit to generate a second feedback voltage with an amplitude that is a fraction of the voltage of the control terminal, and a regulator circuit to regulate the first feedback voltage according to the second feedback voltage by controlling a first input current of the first circuit and a second input current of the second circuit.

Abstract: Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.

Abstract: A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function(Vtp,Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp,Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, where the vector comprises data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations. The one or more actions comprise modifying the data values representing information for a packet. The block also comprises at least one stateful memory comprising stateful memory data values. The one or more actions includes various stateful actions for reading stateful memory, modifying data values representing information for a packet, as a function of the stateful memory data values; and storing modified stateful memory data value back into the stateful memory.

Abstract: Several techniques aimed at reducing computational complexity when encoding uses bi-predictively encoded frames (B-frames) are implemented in a video encoder. In an embodiment, B-frames are not used as reference frames for encoding P-frames and other B-frames. Non-use of B-frames allows a de-blocking filter used in the video encoder to be switched off when reconstructing encoded B-frames, and use of a lower complexity filter for fractional-resolution motion search for B-frames. In another embodiment, cost functions used in motion estimation for B-frames are simplified to reduce computational complexity. In one more embodiment, fractional pixel refinement in motion search for B-frames is simplified. In yet another embodiment, predictors used in motion estimation for a macro-block in a P-frame are selected from a B-frame that uses a same reference frame as the P-frame.

Abstract: In some embodiments, a computer-readable medium stores executable code, which, when executed by a processor, causes the processor to: capture an image of a finder pattern using a camera; locate a predetermined point within the finder pattern; use the predetermined point to identify multiple boundary points on a perimeter associated with the finder pattern; identify fitted boundary lines based on the multiple boundary points; and locate feature points using the fitted boundary lines.

Abstract: An analog-to-digital converter including a first stage and a second stage. The first stage includes a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output. The first stage also includes a buffer, a first flash converter and a first digital-to-analog converter (DAC). The buffer has an input coupled to the first SH output and has a buffer output. The first flash converter has an input coupled to the first SH output, and has a first flash converter output. The first DAC has an input coupled to the first flash converter output. The second stage includes a second flash converter having an input coupled to the buffer output.

Abstract: A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

Abstract: A device such as a portable computing/communications device is configured with slotted touch-on-metal buttons integrated into an edge panel. A ToM button structure includes a structural fascia integrated into the edge panel, defining a touch-button area including a touch-button length. The structural fascia is slotted, with alternating sections that are respectively relatively-thinner and relatively-thicker. The ToM button can be integrated into curved for flat edge panels. Button-press detection can be based on, for example, either inductive and capacitive deformation sensing. The ToM button structure can be configured for a predetermined button-press deformation based on a defined touch-button length, defined slotting difference between the relatively-thinner sections and the relatively-thicker sections and a defined deformation pressure.

Abstract: Methods and apparatus to provide a high-efficiency drive for a floating gate are disclosed. An example apparatus includes a driver including a supply terminal, the driver configured to output a third voltage corresponding to the supply terminal, the driver to drive a gate of a transistor in a power converter; and a second capacitor to be charged using a first discharging current of a first capacitor and discharged at the supply terminal of the driver, the driver to drive the gate of the transistor based on a second discharging current from the second capacitor.

Abstract: An embodiment includes a method and an encoder for SSIM-based bits allocation. The encoder includes a memory and a processor utilized for allocating bits based on SSIM, wherein the processor estimates the model parameter of SSIM-based distortion model for the current picture and determines allocates bits based on the SSIM estimation.

Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

Abstract: A level shifter includes a signal generator that generates differential signals on a first output and a second output. A first capacitor is coupled between the first output and a first node and a second capacitor is coupled between the second output and a second node. A third capacitor is coupled between the first node and a first voltage potential, wherein the capacitance of the third capacitor is variable. A fourth capacitor is coupled between the second node and the first voltage potential, wherein the capacitance of the fourth capacitor is variable.

Abstract: A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.

Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.