Abstract: A control circuit for a DC-DC converter and a DC-DC converter are disclosed. The control circuit includes an integrator coupled to receive a first reference voltage and a first voltage that includes an output voltage for the DC-DC converter and to provide an integrated error signal. A first comparator is coupled to receive the first reference voltage and the first voltage and to provide a dynamic-integration signal that adjusts the integration time constant of the integrator.

Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole.

Abstract: The pupil formed by an optical apparatus is expanded by use of a beam splitter to replicate the pupil and a waveguide to further replicate the replicated pupil. An optional rotator element can rotate a portion of the light split by the beam splitter to provide consistent polarization of light in the optical apparatus. In some embodiments, the beam splitter replication expands the pupil in one direction, while the waveguide replication expands the pupil in a second direction.

Abstract: Multiple transform sizes improve video coding efficiency, but also increase the implementation complexity. Furthermore, both forward and inverse transforms need to be supported in various consumer devices. Embodiments provide a unified forward and inverse transform architecture that supports computation of both forward and inverse transforms for multiple transforms sizes using shared hardware circuits. The unified architecture exploits the symmetry properties of forward and inverse transform matrices to achieve hardware sharing across the different transform sizes and also between forward and inverse transform computations.

Abstract: A wireless receiver (10) includes a down converter module (210) operable to deliver a signal having a signal bandwidth that changes over time, a dynamically controllable filter module (200) having a filter bandwidth and fed by said down converter module (210), and a measurement module (295) operable to at least approximately measure the signal bandwidth, said dynamically controllable filter module (200) responsive to said measurement module (295) to dynamically adjust the filter bandwidth to more nearly match the signal bandwidth as it changes over time, whereby output from said filter module (200) is noise-reduced. Other wireless receivers, electronic circuits, and processes for their operation are disclosed.

Abstract: A low power radio frequency (RF) signal detector comprising a set of transistors, a bias input circuitry configured to apply bias to each of the set of transistors, and a differential signal input circuitry configured to apply a pair of differential signals to the set of transistors, wherein the pair of differential signals increases or decreases bias applied to the set of transistors to achieve low power, high frequency RF signal detection.

Abstract: An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.

Abstract: Disclosed examples include image processing methods and systems to process image data, including computing a plurality of scaled images according to input image data for a current image frame, computing feature vectors for locations of the individual scaled images, classifying the feature vectors to determine sets of detection windows, and grouping detection windows to identify objects in the current frame, where the grouping includes determining first clusters of the detection windows using non-maxima suppression grouping processing, determining positions and scores of second clusters using mean shift clustering according to the first clusters, and determining final clusters representing identified objects in the current image frame using non-maxima suppression grouping of the second clusters.

Abstract: A bandgap voltage circuit with a first circuit to generate an output voltage as a sum of a first voltage with an amplitude that is proportional to absolute temperature, and a first feedback voltage with an amplitude that is complementary to absolute temperature, a second circuit to generate a voltage having an amplitude that is complementary to absolute temperature, a scaling circuit to generate a second feedback voltage with an amplitude that is a fraction of the voltage of the control terminal, and a regulator circuit to regulate the first feedback voltage according to the second feedback voltage by controlling a first input current of the first circuit and a second input current of the second circuit.

Abstract: One example includes a relay device that is comprised of a galvanic isolation barrier, a protection control and power extractor, and an electronic switch. The galvanic isolation barrier is coupled to an input of the relay device and receives a switch control signal and outputs another switch control signal. The protection control and power extractor is coupled to an output of the galvanic isolation barrier. The protection control and power extractor extracts power from a power supply coupled to the relay device. The protection control and power extractor is responsive to the other switch control signal and generates a protection signal in response to a determination of an operating parameter of the relay device. The protection control and power extractor further outputs an electronic switch device signal based on the generated protection signal.

Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.

Abstract: A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.

Abstract: A method for pseudo channel hopping in a node of a wireless mesh network is provided that includes scanning each channel of a plurality of channels used for packet transmission by the node, wherein each channel is scanned for a scan dwell time associated with the channel, updating statistics for each channel based on packets received by the node during the scanning of the channel, and changing scan dwell times of the plurality of channels periodically based on the statistics.

Abstract: An apparatus includes an alternating current (AC) input node. The apparatus also includes a power factor correction (PFC) circuit with a first inductor coupled between the AC input node and a switch node. The apparatus also includes a switching analysis circuit for the PFC circuit. The switching analysis circuit includes a second inductor inductively coupled to the first inductor. The switching analysis circuit also includes a rectifier coupled to the second inductor. The switching analysis circuit also includes a sensing resistor coupled to the rectifier.

Abstract: In a described example, an apparatus includes: transistor having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a gate terminal; a temperature sensor configured to sense a junction temperature of the transistor and generate a temperature signal based on the sensed junction temperature; and a gate driver circuit configured to generate a gate signal based on the temperature signal and to output the gate signal to the gate terminal of the transistor.

Abstract: A circuit includes a phase and frequency detector circuit to generate a first phase detect signal indicative of whether a polarity of a first clock is the same as a polarity of a second clock upon occurrence of an edge of a data signal. The second clock being 90 degrees out of phase with respect to the first clock. A lock detect circuit determines, based on the first phase detect signal, that a third clock is one of frequency and phase locked to the data signal, frequency and quadrature locked to the data signal, and not frequency locked to the data signal.

Abstract: Disclosed embodiments relate to one or more techniques to control access by a requestor of a computing system to a shared memory resource. In one embodiment, a technique includes determining a number (N) of pending requests to be sent to the memory by the requestor, determining a number (M) of requests that the requestor is limited to sending based on an amount of buffering resources available, and comparing M to N. When N is both greater than zero and less than or equal to M, the requestor sends the N pending requests to the memory. When N is both greater than zero and greater than M, M is compared to a hysteresis value (R) and, when M is less than R, the requestor sends R of the N pending requests to the memory.

Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.

Abstract: Synchronized media streaming in a device chain including first, second and third Bluetooth media device having a controller and time synchronization algorithm. The first device formats a first media packet including received media data, second device address, and synchronization information including packet start time including a delay time and cumulative clock drift counted thus far. The second device receives the first packet and formats a second packet including the media data, third device address, updated synchronization information including the second packet's play start time, local clock time, clock drift, and a cumulative clock drift counted thus far. The second device transmits the second packet to the third device. The synchronization algorithms begin synchronized playing of the media data including the first device playing after the delay time, second device playing after the first packet's play start time, and the third device playing after the second packet's play start time.

Abstract: An automotive system includes a battery and a switching converter circuit. The switching converter circuit includes an output inductor estimator circuit coupled to a driver and a switch node of the switching converter circuit. The output inductor estimator circuit is configured to estimate inductance for an output inductor based on a comparison of sampled voltages from the switch node with voltage error values obtained using an adjustable estimated inductance parameter. The output inductor estimator circuit is configured to provide a signal indicating the estimated inductance for the output inductor.