Abstract: In at least some embodiments, a communication device includes a transceiver with a physical (PHY) layer. The PHY layer is configured for body area network (BAN) operations in a limited multipath environment based on a constant symbol rate for BAN packet transmissions and based on M-ary PSK, differential M-ary PSK or rotated differential M-ary PSK modulation. The PHY layer is configured to construct a physical-layer service data unit (PSDU) based on a concatenate block, an insert shortened bits block, a Bose, Ray-Chaudhuri, Hocquenghem (BCH) encoder, a remove shortened bits block, an add pad bits block, a spreader, a bit interleaver, a scrambler, and a symbol mapper.

Abstract: Embodiments of the invention provide a system and method of hybrid automatic repeat-request (HARQ) processing. A viterbi decoder is coupled to and follows a descrambler. After the signal has been de-scrambled, it can be stored in a memory in case it needs to be recombined with another packet. This means that the log-likelihood ratios LLRs for each transmitted bit are stored in memory using a finite number of bits (for example, between 4 and 12 bits). If the packet that is currently being processed contains retransmitted information, then the de-scrambled output stored from a previous packet containing the same information can be loaded and combined with the current packet.

Abstract: A method for compensating an automatic white balance (AWB) reference generated for a first image sensor is provided that includes computing a red adjustment factor, a green adjustment factor, and a blue adjustment factor based on an average red value, an average green value, and an average blue value of the first image sensor and an average red value, an average green value, and an average blue value of a second image sensor, and modifying a red value, a green value, a blue value, and chromaticity values of the AWB reference based on the red adjustment factor, the green adjustment factor, and the blue adjustment factor to generate a compensated reference for the second image sensor. A method for tuning AWB references based on changes in chromaticity values of the references is also provided.

Abstract: Image noise reduction filtering by low-pass/high-pass filtering to get a hierarchical representation, modifying coefficients in each hierarchy level for noise suppression, and the modified level combination to yield a noise-filtered image. The noise suppression within levels preserves edges which the representation preserves.

Abstract: Random access decoding start points (audio frame headers) for AMR-type files are found by sequential elimination of types of file points from consideration for a block of file points following a random access selected point. Chaining of file points according to frame header format interpretation gives paths of points through the block, and selection of maximal path(s) includes sums of weights of the points of a path. The next-to-initial points of such a maximal path provides a decoding start point.

Abstract: In an I/O driver, noise reduction is achieved while maintaining good performance, by providing a conventional output driver leg and a secondary output driver leg, the primary output driver leg comprising a primary predriver and a primary output driver, and the secondary output driver leg comprising a secondary output driver having a common output with the primary output driver, wherein feedback from the common output is fed through a pair of pass gates that control the secondary output driver.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A system and method for controlling a sound level of a mobile audio device are disclosed herein. In accordance with at least some embodiments, a system includes a transducer, a phase estimator, and a sound level control. The transducer converts an electrical signal applied to the transducer into audible sound. The phase estimator estimates a phase difference between a voltage and a current of the electrical signal applied to the transducer. The sound level control controls the loudness of sound produced by the transducer based, at least in part on the estimated phase difference.

Abstract: An SRAM device and method of forming MOS transistors of the device having reduced defects associated with selective epitaxial growth in moat tip regions is discussed. The SRAM device comprises a core region and a logic region, logic transistors within the logic region of the SRAM, and selective epitaxial regions grown on both source and drain regions; and memory cell transistors within the core region of the SRAM, and having the selective epitaxial regions grown on only one of the source and drain regions. One method of forming the MOS transistors of the SRAM cell comprises forming a gate structure over a first conductivity type substrate to define a channel therein, masking one of the source and drain regions in the core region, forming a recess in the substrate of the unmasked side of the channel, epitaxially growing SiGe in the recess, removing the mask, and forming the source and drain extension regions in source/drain regions.

Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.

Abstract: A circuit for controlling temperature of a semiconductor chip includes a first heating element that is built into the semiconductor chip. The first heating element generates heat to increase the temperature of the semiconductor chip. The chip also includes a temperature controller that is coupled to the first heating element and built into the semiconductor chip. The temperature controller controls the temperature to enable testing of the semiconductor chip at a desired temperature.

Abstract: An integrated circuit that includes a logic region, a buffer region, and a ferroelectric capacitor region that contains ferroelectric capacitors. The integrated circuit also includes a hydrogen diffusion barrier film that overlies ferroelectric capacitors and also overlies a buffer region located between a ferroelectric capacitor region and a logic region. However, the hydrogen diffusion barrier film is removed from a portion of the logic region. Moreover, a method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.

Abstract: A soft-error resistant redundant latch including a first stage and second stage, each stage coupled to receive and to latch a binary signal in a latched state. Each stage is arranged to maintain the latched state at an intermediary node of the stage in response to a feedback path internal to the stage and in response to a stage output signal from the other stage. Each stage is arranged to generate a stage output signal in response to the latched state of the stage. The state of each stage is set to a first selected state by selectively coupling a stage set transistor between a first power rail and the intermediary node of the first stage in response to a set signal. The stage set transistor of the first stage and the stage set transistor of the second stage are complementary types.

Abstract: A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output.

Abstract: Methods of connecting solder bumps located on dies to leads located on substrates are disclosed herein. One embodiment includes applying a first compression force between the solder bump and the lead; relieving the first compression force between the solder bump and the lead; and applying a second compression force between the solder bump and the lead.

Abstract: A phase delay element coupled to an output of A multiplexor and a first input of the multiplexor. A reference clock line is coupled to a second input of the multiplexor. A selector that is coupled to a selector input of the multiplexor. A signal divider element coupled to an output of the phase delay element. A variable delay controller is coupled to a) the output of the variable delay controller; b) at least one output of the variable delay controller. An integrated phase detector and charge pump element (PDCHP) is coupled to at least: a) an output of the variable delay controller; and b) the selector; c) and a first and second output of the divider element. A capacitor is coupled to an output of the PDCHP, wherein the capacitor is also coupled to a controller input of the phase delay element.

Abstract: This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention selects a set of the finite state machines to participate in an operation. If one or more of the finite state machines are selected for operation, the method waits until all selected finite state machines generate the ready signal. If none of the finite state machines are selected for operation, the method waits until at least one non-selected finite state machine generates the ready signal. This waiting can be accomplished with a precharge-conditional discharge circuit used for voting.

Abstract: The high resolution capture (HRCAP) of this invention enables time stamping of input signals with very high resolution without requiring high frequency sampling. This invention uses a capture delay line to time stamp an input edge signal as a fraction of the input signal sampling frequency. The capture delay line includes a first input receiving a synchronized signal and a second input receiving the input signal. These inputs propagate toward one another within a sequence of bit circuits. The meeting location within the sequence of bit circuits indicates a time of the input signal transition at a resolution greater than possible via the sampling frequency clock.

Abstract: An embodiment of the invention provides a method for continuously detecting when a USB client device may be charged according to a BCS charging standard. Power is supplied from a USB host device to the USB client device with a first current limit. Next, the USB host device monitors data lines D+ and D? for a first part of a handshake. When the first part of the handshake is detected, a second part of the handshake is provided by the USB host device indicating that the USB client device may be changed according to the BCS charging standard. All current sources and all voltage sources that are coupled to the data lines D+ and D? are decoupled from data lines D+ and D? after the handshake is complete. After the data lines are decoupled, communication may begin between the USB host device and the USB client device.