Abstract: An IC magazine with retractable stop pins at both ends of the IC magazine. The retractable stop pins project into the magazine slot through an opening from a cavity in the base of the IC magazine. The long segment of an L-shaped push rod projects through an opening from the cavity through the magazine rail. The short segment of the L-shaped push rod is coupled to the bottom of the retractable stop pin inside the cavity. A spring inside the cavity between the underside of the short segment and the bottom of the cavity holds the retractable stop pin in an up position. An IC magazine with retractable stop pins at both ends of the IC magazine. The retractable stop pins project into the magazine slot through an opening from a cavity in the base of the IC magazine. A stop collar surrounding the retractable stop pin inside the cavity. A spring inside the cavity that pushes up on the underside of the stop collar and pushes down on the bottom of the cavity.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.

Abstract: A gate drive adapter circuit includes an input circuit, an output circuit, and a charge pump circuit. The input circuit is configured to receive pulses suitable for controlling a silicon power transistor. The output circuit is coupled to the input circuit. The output circuit is configured to translate the pulses to voltages suitable for controlling a silicon-carbide power transistor. The charge pump circuit is coupled to the input circuit and to the output circuit. The charge pump circuit is configured to generate a negative voltage. The output circuit is configured to apply the negative voltage to translate the pulses.

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

Abstract: A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the execution pipeline.

Abstract: Some embodiments are directed to an anisotropic magneto-resistive (AMR) angle sensor die. The die comprises a plurality of AMR angle sensors, each of the plurality of AMR angle sensors comprising a first Wheatstone bridge and a second Wheatstone bridge, wherein an angle position output of the sensor die includes a combination of angle position outputs of each of the plurality of AMR angle sensors.

Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (?d) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using ?d to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.

Abstract: An integrated circuit containing SRAM cells. Each SRAM cell has a PMOS driver transistor, a PMOS passgate transistor, and at least two separate n-wells. The integrated circuit also has an n-well bias control circuit that is configured to independently bias the n-wells of an addressed SRAM cell. Moreover, a process of operating an integrated circuit that contains SRAM cells. The process includes writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell.

Abstract: A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Abstract: A method for luma-based chroma intra-prediction in a video encoder or a video decoder is provided that includes down sampling a first reconstructed luma block of a largest coding unit (LCU), computing parameters ? and ? of a linear model using immediate top neighboring reconstructed luma samples and left neighboring reconstructed luma samples of the first reconstructed luma block and reconstructed neighboring chroma samples of a chroma block corresponding to the first reconstructed luma block, wherein the linear model is PredC[x,y]=?·RecL?[x,y]+?, wherein x and y are sample coordinates, PredC is predicted chroma samples, and RecL? is samples of the down sampled first reconstructed luma block, and wherein the immediate top neighboring reconstructed luma samples are the only top neighboring reconstructed luma samples used, and computing samples of a first predicted chroma block from corresponding samples of the down sampled first reconstructed luma block using the linear model and the parameters.

Abstract: Disclosed examples include a transient event detector circuit to detect transient events in a switching converter, including a DLL circuit to detect changes in a duty cycle of a pulse width modulation signal used to operate a switching converter, and an output circuit to provide a status output signal in a first state when no transient event is detected, and to provide the status output signal in a second state indicating a transient event in the switching converter in response to a detected change in the duty cycle of the pulse width modulation signal.

Abstract: A switching converter having a high-side switching transistor and a low-side switching transistor and an inductor, having a circuit for generating a simulated waveform representing a sawtooth inductor current waveform. A circuit for monitoring and voltage at a switch node between the high-side and low-side transistors to determine a time during which the inductor current is increasing and a time during which the inductor current is decreasing wherein voltage across the low-side transistor when it is conducting represents a first portion of the simulated sawtooth inductor current waveform. A circuit for utilizing the time when the inductor current is increasing, the time when the inductor current is decreasing and the voltage across the low-side transistor when it is conducting to generate a portion of the simulated inductor current waveform when the high-side transistor is conducting. A method and a power supply utilizing this circuit are also disclosed.

Abstract: In the described examples, a non-transitory machine-readable medium includes a compiler that detects a soft-break indicator in a loop included in source code and the compiler applies software pipelining to generate compiled code for the loop. The compiled code includes assembly instructions and the soft-break indicator enables the compiler to arrange the assembly instructions to complete in-flight iterations of the loop after execution of the soft-break.

Abstract: A system includes a monitored component and a comparator configured to compare a sense voltage from the monitored component with a reference voltage. The system also includes an adaptive input clamping circuit configured to limit the sense voltage input to the comparator to below an upper threshold voltage.

Abstract: A voltage protection circuit, comprising a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to a first node, a source terminal coupled to a second node, and a drain terminal coupled to a third node, a second MOSFET having a gate terminal coupled to the first node, a source terminal coupled to the second node, and a drain terminal coupled to a fourth node, a first current mirror coupled to the third node and configured to couple to a fifth node, a sixth node, and a regulator supply, and a second current mirror coupled to the fourth node, and configured to couple to the fifth node, the sixth node, and a ground node.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. First and second wells are located within the substrate, the first well being formed with a dopant of the first conductivity type, e.g. n-type, and the second well formed with a dopant of a second different conductivity type, e.g. p-type. A doped gap region is located between the first and second wells. The doped gap region is formed with a dopant of the second conductivity type, e.g. p-type, at a lower dopant concertation than the dopant concentration in the second well.

Abstract: A power circuit with a first transistor, including a first terminal connected to a first node, a second terminal connected to an input node, and a control terminal connected to a first control node, and a second transistor, including a first terminal connected to the first node, a second terminal connected to an output node, and a control terminal connected to a second control node. A third transistor includes a first terminal connected to the first control node, a second terminal connected to a second node, and a control terminal, and a fourth transistor includes a first terminal connected to the output node, a second terminal connected to the second control node, and a control terminal connected to a third node. The power circuit also includes a current limiting circuit coupled between the second node and the third node.

Abstract: An integrated circuit (IC) chip for providing a safety-critical value includes first and second processing paths. The first processing path includes a first processing element and is coupled to receive a first input signal on a first input pin and to provide a first output signal that provides the safety-critical value on an output pin. The second processing path includes a second processing element and is coupled to receive a second input signal and to provide a second output signal. The first processing path and the second processing path are independent of each other. A smart comparator on the IC chip receives the first output signal and the second output signal and initiates a remedial action responsive to a difference between the first output signal and the second output signal reaching a configurable threshold.

Abstract: An encapsulated integrated circuit that includes an integrated circuit (IC) die and an encapsulation material encapsulating the IC die. A first portion of the encapsulation material is solid and a second portion of the encapsulation material includes spaces filled with a second material.