Patents Assigned to Texas Instruments
  • Current sensing and control for a transistor power switch
    Patent number: 10361695
    Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Ankur Chauhan, Sudheer Prasad, Md. Abidur Rahman, Subrato Roy
  • ID-based control unit-key fob pairing
    Patent number: 10358113
    Abstract: A method for pairing a key fob with a control unit is provided. The key fob executes an ID authenticated key agreement protocol with a pairing device based on a key fob identification to authenticate one another and to generate a first encryption key. The pairing device encrypts a control unit identification using the first encryption key. The key fob receives the encrypted control unit identification transmitted from the pairing device. The key fob then executes an ID authenticated key agreement protocol with the control unit based on the control unit identification to authenticate one another and to generate a second encryption key. The key fob then receives an operational key transmitted from the control unit that is encrypted with the second encryption key.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: July 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jin-Meng Ho, Eric Peeters
  • Methods for converting circuits in circuit simulation programs
    Patent number: 10360328
    Abstract: A method for converting a circuit in a format of a first circuit simulation program to format of a second circuit simulation program includes identifying components in the circuit that are recognized by the second simulation program. Characteristics for components that are not recognized by the second simulation program are created. Connections in the circuit are formatted to a format that is recognized by the second simulation program. The components, characteristics, and connections are stored in a single computer-readable file.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: July 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pradeep Kumar Chawda, Makram Mansour, Satyanandakishore Vanapalli, Ashwin Vishnu Kamath, Kian Haur Chong, Dien Mac, Jeff Perry
  • Two-wire communication interface system
    Patent number: 10361838
    Abstract: One example includes a master microcontroller in a communication interface system. The microcontroller includes a transmitter configured to generate a clock signal at a selected frequency and to provide the clock signal to a slave microcontroller on a two-wire communication cable during a clock learning mode. The transmitter can be further configured to provide master data signal requests at the selected frequency on the two-wire communication cable during a data transfer mode. The microcontroller also includes a receiver configured to receive slave data signals at the variable frequency via the two-wire communication cable in response to the master data signal requests during the data transfer mode.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Subrahmanya Bharathi Akondy
  • Architecture and instruction set to support integer division
    Patent number: 10359995
    Abstract: A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: July 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alexander Tessarolo, Prasanth Viswanathan Pillai, Venkatesh Natarajan
  • 4Tx codebook enhancement in LTE
    Patent number: 10361760
    Abstract: Channel state information (CSI) feedback in a wireless communication system is disclosed. A precoding matrix is generated for multi-antenna transmission based on precoding matrix indicator (PMI) feedback, wherein the PMI indicates a choice of precoding matrix derived from a matrix multiplication of two matrices from a first codebook and a second codebook. In one embodiment, the first codebook comprises at least a first precoding matrix constructed with a first group of adjacent Discrete-Fourier-Transform (DFT) vectors. In another embodiment, the first codebook comprises at least a second precoding matrix constructed with a second group of uniformly distributed non-adjacent DFT vectors.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: July 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eko Onggosanusi, Runhua Chen, Ralf Bendlin
  • Thin film resistor with punch-through vias
    Patent number: 10354951
    Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: July 16, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
  • Methods and apparatus for narrowband ranging systems using reference signal interpolation
    Patent number: 10353062
    Abstract: Methods and apparatus to determine an accurate distance to a target using reference signal interpolation is disclosed. An example apparatus includes an interpolator to receive a first sample of a reference signal and a second sample of a reference signal; and interpolating a reconstructed reference signal sample based on the first and second samples, the reconstructed reference signal corresponding to the reference signal; a correlator to generate a plurality of phase-shifted, reconstructed reference signals; and correlate each of the plurality of phase-shifted, reconstructed reference signals with a reflected signal; and an optimal phase selector to determine an optimal phase based on the correlations and output a distance to a target based on the optimal phase.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nirmal C. Warke, David P. Magee
  • Stationary-vehicle structure from motion
    Patent number: 10354149
    Abstract: A vehicular structure from motion (SfM) system can store a number of image frames acquired from a vehicle-mounted camera in a frame stack according to a frame stack update logic. The SfM system can detect feature points, generate flow tracks, and compute depth values based on the image frames, the depth values to aid control of the vehicle. The frame stack update logic can select a frame to discard from the stack when a new frame is added to the stack, and can be changed from a first in, first out (FIFO) logic to last in, first out (LIFO) logic upon a determination that the vehicle is stationary. An optical flow tracks logic can also be modified based on the determination. The determination can be made based on a dual threshold comparison to insure robust SfM system performance.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prashanth Ramanathpu Viswanath, Soyeb Nagori, Manu Mathew
  • Multilevel boost DC to DC converter circuit
    Patent number: 10355591
    Abstract: Described examples include DC to DC converters and systems with switching circuitry formed by four series-connected switches, inductors connected between the ends of the switching circuitry and corresponding output nodes, and with a flying capacitor coupled across interior switches of the switching circuitry and a second capacitor coupled across the ends of the switching circuitry. A control circuit operates the switching circuit to control a voltage signal across the output nodes using a first clock signal and a phase shifted second clock signal to reduce output ripple current and enhance converter efficiency using valley current control. The output inductors are wound on a common core in certain examples.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Maurizio Granato, Giovanni Frattini, Pietro Giannelli, Michael Lueders, Christian Rott
  • Voltage step-down technique for deriving gate-charge using multi-level core architecture
    Patent number: 10355609
    Abstract: In described examples of methods and control circuitry to control a multi-level power conversion system with a flying capacitor, a power circuit regulates a regulator input voltage signal to provide a supply voltage signal to the control circuitry. A power switching circuit couples the regulator input to a first terminal of the flying capacitor in response to a second terminal of the flying capacitor being coupled to a reference voltage node in a given switching cycle, and couples the regulator input to the second terminal in response to the first terminal being coupled to an input node of the power conversion system in the given switching cycle.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Orlando Lazaro, Kevin Scoones, Jeffrey Anthony Morroni, Alvaro Aguilar, Reza Sharifi
  • Low power zero inductor current detection circuit
    Patent number: 10355592
    Abstract: Methods and apparatus for detecting a zero inductor current to control switch transitions for a power converter. An example method includes outputting a first voltage and a first current, receiving the first voltage and output a second voltage into an input of a comparator, when the second voltage is above a third voltage, outputting a first output voltage, when the second voltage is below the third voltage, outputting a second output voltage, determining when the first current is zero based the output of the comparator, enabling a set of switches based on when the first current is zero.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ranjit Kumar Dash, Keith Edmund Kunz
  • Integrated force sensing element
    Patent number: 10353503
    Abstract: An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element may include a conditioning circuit, temperature gauge, FRAM and a processor core.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Wei-Yan Shih, Steve Kummerl, Mark Stephen Toth, Alok Lohia, Terry Lee Sculley, Seung Bae Lee, Scott Robert Summerfelt
  • Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making
    Patent number: 10353823
    Abstract: An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130). The processor (130) is coupled to the on-chip boot ROM (132) and to the non-volatile security identification element (140) to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element (140). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charles W. Brokish, Narendar Madurai Shankar, Erdal Paksoy, Steve Karouby, Olivier Schuepbach
  • Process for forming PZT or PLZT thinfilms with low defectivity
    Patent number: 10354858
    Abstract: Use of a non-solvent for the edge bead removal of spin-coated PZT or PLZT thinfilms, eliminates swelling of the exposed edges of the PZT or PLZT thinfilms and eliminates delamination and formation of particle defects in subsequent bake and anneal steps.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Asad Mahmood Haider, John Britton Robbins
  • Bandgap reference circuit with inverted bandgap pairs
    Patent number: 10353414
    Abstract: In some examples, a bandgap reference circuit comprises a first bandgap pair having multiple first diodes and a first resistor positioned between the multiple first diodes. The circuit also comprises a second bandgap pair having multiple second diodes and a second resistor positioned between the multiple second diodes, the second bandgap pair being an inverted form of the first bandgap pair. The circuit further comprises a scaling resistor coupled to the first and second bandgap pairs. The circuit still further comprises an operational amplifier coupled to the first and second bandgap pairs.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sandeep Shylaja Krishnan
  • Packaged semiconductor device having nanoparticle adhesion layer patterned into zones of electrical conductance and insulation
    Patent number: 10354890
    Abstract: A device comprises a substrate and an adhesive nanoparticle layer patterned into zones of electrical conductance and insulation on top of the substrate surface. A diffusion region adjoining the surface comprises an admixture of the nanoparticles in the substrate material. When the nanoparticle layer is patterned from originally all-conductive nanoparticles, the insulating zones are created by selective oxidation; when the nanoparticle layer is patterned from originally all-non-conductive nanoparticles, the conductive zones are created by depositing selectively a volatile reducing agent. A package of insulating material is in touch with the nanoparticle layer and fills any voids in the nanoparticle layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Yong Lin
  • Low substrate leakage zener diode with modulated buried junction
    Patent number: 10355076
    Abstract: In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jun Cai, Binghua Hu
  • Device and method for on-chip mechanical stress sensing
    Patent number: 10352792
    Abstract: An integrated circuit (IC) chip includes a substrate of a piezo-electric material having a first resistivity coefficient associated with a first direction that is longitudinal to a first crystal axis and a second resistivity coefficient associated with a second direction that is transverse to the first crystal axis. The first and second resistivity coefficients have opposite signs. The IC chip also includes a first stress sensing element formed in the substrate and coupled to pass a first current therethrough. The first stress sensing element includes a first resistor aligned such that the major direction of current flow through the first resistor is in the first direction and a second resistor coupled in series with the first resistor and aligned such that the major direction of current flow through the second resistor is in the second direction.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Umidjon Nurmetov, Ralf Peter Brederlow, Baher Haroun
  • Distributed procedure for breadth-first graph traversal on asymmetric communication topologies
    Patent number: 10355970
    Abstract: The breadth-first search (BFS) starts with a root node. In the first stage, all neighbors of the root node are discovered and added to the nodes frontier. In the following stages, unvisited nodes from the neighbors of the frontier nodes are discovered and added to the frontier. To improve the parallelization of the BFS, the bottom-up search iterates over all unvisited nodes, where each unvisited node searches for its visited neighbors. Communication between nodes and clusters is pipelined with the execution of the BFS.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mohamed Farouk Mansour