Abstract: A method includes applying a die attach material to a die pad of an integrated circuit. The die attach material is employed as a bonding material to the die pad. The method includes mounting an integrated circuit die to the die pad of the integrated circuit via the die attach material. The method includes printing an adhesion deposition material on the die attach material appearing at the interface of the integrated circuit die and the die pad of the integrated circuit to mitigate delamination between the integrated circuit die and the die pad.

Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.

Abstract: A microcontroller-based system for identifying a paper type of a sample of paper from a measurement of its electrical impedance. An interdigital dielectric sensor (55) is deployed in the paper path of a printer (PTR), and the electrical impedance at the sensor, as affected by a sheet of paper (P) near the sensor, is measured over a plurality of frequencies of a stimulus signal. The stimulus signal may be sinusoidal or a square wave. The impedance characteristic, in magnitude or phase, or both, is compared against a plurality of reference impedance characteristics, each associated with a paper type, to identify the closest match and thus the type of paper of the sample sheet.

Abstract: A system and method for providing both localized and distributed transmission modes for EPDCCH is disclosed, where one EPDCCH comprises of one or multiple CCEs. Localized versus distributed transmission may be defined in terms of the EPDCCH to CCE resource mapping. In a localized transmission CCEs are restricted to be contained within one PRB. In a distributed transmission a CCE spans over multiple PRBs. A UE can be configured to either receive the EPDCCH only in localized or only in distributed transmissions. A UE can also be configured to expect EPDCCH transmissions in both localized and distributed transmissions. In each PRB configured by the higher layer as an EPDCCH resource, 24 REs that may be used for any DMRS transmission are always reserved and not used for EPDCCH transmission.

Abstract: An assembly (101) comprising a semiconductor device (110) with solderable bumps (112); a substrate (120) with a layer (130) of a first insulating compound and an underlying metal layer (140) patterned in contact pads (141) and connecting traces (142), the insulating layer having openings (132) to expose the surface (142a) and sidewalls (142b) of underlying traces; the device bumps soldered onto the contact pads, establishing a gap (150) between device and top insulating layer; and a second insulating compound (160) cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.

Abstract: An integrated fluxgate device has a magnetic core on a control circuit. The magnetic core has a volume and internal structure sufficient to have low magnetic noise and low non-linearity. A stress control structure is disposed proximate to the magnetic core. An excitation winding, a sense winding and a compensation winding are disposed around the magnetic core. An excitation circuit disposed in the control circuit is coupled to the excitation winding, configured to provide current at high frequency to the excitation winding sufficient to generate a saturating magnetic field in the magnetic core during each cycle at the high frequency. An isolation structure is disposed between the magnetic core and the windings, sufficient to enable operation of the excitation winding and the sense winding at the high frequency at low power.

Abstract: One example includes a power supply system. The system includes a switch system comprising a switch that is configured to generate a switching voltage at a switching node in response to an input voltage. The system also includes a non-linear capacitance charge-pump coupled to the switching node and being configured to provide an output current in response to the switching voltage. The output current can have an amplitude that varies non-linearly with respect to an amplitude of the switching voltage. The switch system further includes an output stage configured to generate an output voltage on an output node in response to the output current.

Abstract: An integrated circuit is provided with a bandgap voltage reference circuit having a bandgap reference voltage output. A bandgap failure detection circuit is coupled to the bandgap reference voltage output. The bandgap failure detection forms a model value of the reference voltage from a first time, compares a present value of the reference voltage at a second time to the model value; and asserts a bandgap fail signal to indicate when the present value is less than the model value by a threshold value. The integrated circuit is reset by the bandgap fail signal. The detection circuit may be operated from a failsafe voltage domain that also allows a critical circuit to complete a pending operation during a reset.

Abstract: An example current limiting apparatus comprises a first transistor to carry a first current; a sense transistor coupled to the first transistor, the sense transistor to carry a sense current that is a function of the first current; a first amplifier coupled to the first transistor and the sense transistor, the amplifier to achieve a common voltage potential on terminals of the first and the sense transistors; a second amplifier coupled to the first amplifier and the sense transistor, the second amplifier to control the first and sense transistors based on the sense current; and a circuit coupled to the first and second amplifiers, the circuit to control an input to the second amplifier based on an input to the first amplifier such that a current limit of the first transistor remains below a programmed current limit of the first transistor.

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

Abstract: Embodiments of the invention are directed to a cellular communication network that can determine whether communications between one base station-UE pair may interfere with another UE that is in the same cell or a different cell. The network identifies interference parameters associated with interference signals that may be received by a UE. The interference signals may be generated by the base station itself, such as communications with other UEs, or by a neighboring base station. The base station transmits the interference parameters to the UE. The UE receives the one or more parameters comprising information about signals expected to cause intra-cell or inter-cell interference. The UE then processes received signals using the one or more parameters to suppress the intra-cell or inter-cell interference.

Abstract: A method of entropy coding in a video encoder is provided that includes assigning a first bin to a first single-probability bin encoder based on a probability state of the first bin, wherein the first single-probability bin encoder performs binary arithmetic coding based on a first fixed probability state, assigning a second bin to a second single-probability bin encoder based on a probability state of the second bin, wherein the second single-probability bin encoder performs binary arithmetic coding based on a second fixed probability state different from the first fixed probability state, and coding the first bin in the first single-probability bin encoder and the second bin in the second single-probability bin encoder in parallel, wherein the first single-probability bin encoder uses a first rLPS table for the first fixed probability state and the second single-probability bin encoder uses a second rLPS table for the second fixed probability state.

Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.

Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: This disclosure generally relates to repeaters, and, in particular, repeaters for open-drain systems. In one embodiment, an apparatus comprises a first port, a second port, a current detector, a transistor, and a control logic circuit. A current detector input of the current detector is coupled to the first port. A transistor channel electrode of the transistor is coupled to the second port. A control logic circuit input of the control logic circuit is coupled to the current detector output, and a control logic circuit output of the control logic circuit is coupled to a transistor control electrode of the transistor.

Abstract: A binary signal generator circuit includes a programmable waveform generator (PWG) having an input stage for receiving a digital data stream, a serial clock signal for controlling receipt of the digital data, a frequency synchronization and a clock signal. The PWG includes registers including a first and second register for storing bits representing a first frequency (f1) and for storing bits representing a zero frequency (fo), respectively. A MUX receives a control signal based on the digital data for toggling between bits representing f1 and fo coupled to a digital-to-analog converter (DAC) with an output providing a modulated signal that toggles between essentially f1 and essentially fo. A differential output amplifier receives the modulated signal for generating a first and second amplified signal modulated between essentially f1 and essentially fo. The first and second amplified signal are phase shifted relative to one another, taken together providing a differential signal.

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract: Described examples include devices and methods for measuring relative humidity of an environment using inductance. The devices can include a resonant circuit, including a capacitor and an inductor. The inductor includes a moisture-absorbing core with at least a portion thereof exposed to an environment, with at least one magnetic property of the core being variable in response to changing levels of moisture in the environment. An excitation circuit provides an AC excitation signal to the resonant circuit. A sense circuit determines an inductance of the inductor according to a sense signal from the resonant circuit. The sense circuit is coupled to generate an output signal that indicates a humidity level of the environment according to the sense signal.

Abstract: A microelectronic device includes a photonic die having a die input/output (I/O) port. The microelectronic device includes a photonic connection between the first photonic I/O port and the second photonic I/O port. The photonic connection has a dielectric signal pathway for a photonic signal from the first photonic I/O port to the second photonic I/O port. The second photonic I/O port may be a package photonic I/O port at an exterior of the microelectronic device, or may be another die photonic I/O port on another photonic die of the microelectronic device. The photonic connection is formed using at least one additive process, such as by selectively placing material for the photonic connection in a region for the photonic connection.

Abstract: An integrated circuit having silicide block integrated with CMOS transistors is formed by forming a silicide block layer of primarily silicon dioxide, free of silicon nitride and silicon oxy-nitride, at less than 400° C. prior to annealing the PMOS sources and drains. A spike anneal process concurrently anneals the PMOS sources and drains and densifies the silicide block layer. The NMOS drain junctions are less than 120 nanometers; the NMOS halo regions include boron. The NMOS and PMOS transistors are laterally separated by an STI oxide layer. A wet deglaze process prior to metal silicide formation removes less than 25 percent of the silicide block layer, and exposes sides of the NMOS drains less than 20 percent of the drain junction depth. The metal silicide does not extend down the NMOS drains sides, directly adjacent to the STI oxide layer, more than 20 percent of the drain junction depth.