Abstract: Described examples include a microelectronic device with a high voltage capacitor that includes a high voltage node, a low voltage node, a first dielectric disposed between the low voltage node and the high voltage node, a first conductive plate disposed between the first dielectric and the high voltage node, and a second dielectric disposed between the first conductive plate and the high voltage node.

Abstract: A multi-frequency inductive sensing system can be used for spectrographic material analysis of a conductive target material (such as tissue) based on electrical impedance spectroscopy. An inductive senor can be driven with an excitation current at multiple sensor excitation frequencies (?) to project a time-varying magnetic field into a sensing area on the surface of the target material, inducing eddy currents within the target material. The inductive sensor can be characterized by a sensor impedance Z(?) as a function of the sensor excitation frequency (?), and the resulting induced eddy currents. Multiple sensor impedance Zs(?) measurements, at the multiple sensor excitation frequencies (?), can be determined, which represent electromagnetic properties of the target material (such as permittivity ?, permeability ?, and resistivity ?), based on the induced eddy currents.

Abstract: A DC-to-DC voltage converter includes a converter input for receiving a DC voltage. A first switch is coupled between the input and a first node. A second switch is coupled between the first node and a ground. An inductor is coupled between the first node and a converter output. A capacitor is coupled between the converter output and ground. An output voltage synthesizer is coupled to the converter input and the converter output for synthesizing the voltage at the first node and for generating a control signal for at least one of the first switch and the second switch in response to the voltages at the converter input and the converter output.

Abstract: A high-voltage transistor (HVT) structure adapts a low-voltage transistor (LUT) to high-voltage environments. The HVT structure includes a drain node, a source node, a control gate, and a field electrode. The drain node and the source node define a conductive channel, in which mobilized charges are regulated by the control gate. While being isolated from the control gate, the field electrode is configured to spread the mobilized charges in response to a field voltage. The field electrode is structured and routed to prevent charge sharing with any one of the drain node, source node, or control gate. Advantageously, the isolated field electrode minimizes the capacitance of the control gate as well as the drain and source nodes, such that the HVT can switch with less power loss and a more robust performance in a high-voltage environment.

Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.

Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

Abstract: Low speed and high speed estimates of rotor angle and speed relative to the stator are received from a low speed estimator and a high speed estimator, respectively. LS_?_EST and a subset of torque-controlling I_Q trajectory curve (“IQTC”) parameter values appropriate to low speed rotor operation are selected for rotor speeds below a low speed threshold value ?_LOW_THRS. HS_?_EST and a subset of IQTC curve parameter values appropriate to high speed rotor operation are selected for rotor speeds above a high speed threshold value ?_HIGH_THRS. LS_?_EST and the low speed subset of IQTC parameter values remain selected for rotor speeds less than ?_HIGH_THRS after accelerating to a rotor speed greater than ?_LOW_THRS. HS_?_EST and the subset of high speed IQTC parameter values remain selected for rotor speeds greater than ?_LOW_THRS after decelerating to a rotor speed less than ?_HIGH_THRS.

Abstract: Disclosed examples include an ESD protection circuit to protect an IC pad with high immunity against hot-plug surges, switching noise or other transient voltage conditions on the protected pad. The ESD protection circuit includes a clamp transistor and a trigger circuit responsive to rises in the protected pad voltage at or above a first slew rate to turn on the clamp transistor, as well as a second circuit coupled between the control terminal of the clamp transistor and a voltage supply node. The second circuit responds to rises in a voltage of the clamp transistor control terminal at a second, lower slew rate to reduce the voltage of the first control node to at least partially turn the clamp transistor off to reduce leakage current flow through the clamp transistor during transient voltage conditions on the protected pad.

Abstract: An integrated circuit (IC) comprises an output and a voltage regulator. The voltage regulator comprises an amplifier having a first input coupled to a reference voltage source and a second input coupled to the output, a first resistor coupled to the output and coupled to a ground terminal, a metal oxide semiconductor field effect transistor (MOSFET) having a gate coupled to an output of the amplifier and a drain coupled to the output, and a second resistor coupled to a source of the MOSFET and coupled to the ground terminal.

Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

Abstract: A digital-to-analog converter (DAC) includes a first stage comprising a plurality of first circuit arms coupled together, each first circuit arm including a resistor. A second stage includes a plurality of second circuit arms coupled together, each second circuit arm comprising a first resistor and a pair of series-connected resistors. The first resistors of the second circuit arms are connected in series. A current digital-to-analog converter (IDAC) trim circuit is connected to a plurality, but not all, of the second circuit arms of the second stage. The IDAC trim circuit includes a plurality of first current sources. Each first current source is coupled to a respective node between a pair of the series-connected resistors of a corresponding second circuit arm, and each of the first current sources is configured to produce a same current level as the other first current sources.

Abstract: The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a sampling capacitor coupled to the ADC. The DSA also includes a time dependent resistor coupled to a source voltage and to the sampling capacitor.

Abstract: A successive approximation register analog-to-digital converter with improved kick-back linearization includes a signal input terminal, a capacitive digital-to-analog converter, a first switch, and a second switch. The signal input terminal is configured to receive a signal to be digitized. The capacitive digital-to-analog converter includes a first capacitor array, a second capacitor array, and a coupling capacitor. The first capacitor array includes a plurality of capacitors. The second capacitor array includes a plurality of capacitors. The coupling capacitor connects the first capacitor array to the second capacitor array. The first switch is configured to switchably connect a bottom plate of each of the capacitors of the first capacitor array to the signal input terminal. The second switch is configured to conduct a voltage on the bottom plate of the coupling capacitor to the signal input terminal.

Abstract: A Capacitive Micromachined Ultrasonic Transducer (CMUT) device includes at least one CMUT cell including a first substrate having a top side including a patterned dielectric layer thereon including a thick and a thin dielectric region. A membrane layer is bonded on the thick dielectric region and over the thin dielectric region to provide a movable membrane over a micro-electro-mechanical system (MEMS) cavity. A through-substrate via (TSV) includes a dielectric liner which extends from a bottom side of the first substrate to a top surface of the membrane layer. A top side metal layer includes a first portion over the TSV, over the movable membrane, and coupling the TSV to the movable membrane. A patterned metal layer is on the bottom side surface of the first substrate including a first patterned layer portion contacting the bottom side of the first substrate lateral to the TSV.

Abstract: A method of interconnecting components of a semiconductor device using wire bonding is presented. The method includes creating a free air ball at a first end of an aluminum wire that has a coating surrounding the aluminum wire, wherein the coating comprises palladium, and wherein the free air ball is substantially free of the coating. The method further includes the step of bonding the free air ball to a bond pad on a semiconductor chip, the bond pad having an aluminum surface layer, wherein the resultant ball bond and the bond pad form a substantially homogenous, aluminum-to-aluminum bond. The method may further include bonding a second, opposing end of the coated-aluminum wire to a bond site separate from the semiconductor chip, the bond site having a palladium surface layer, wherein the second end of the coated-aluminum wire and the bond site form a substantially homogenous, palladium-to-palladium bond.

Abstract: An integrated circuit package having a shunt resistor with at least one self-aligning member that protrudes from a first surface, and a lead frame with at least one self-aligning feature that is a cavity within which the at least one self-aligning member is located, and an integrated circuit located on the lead frame.

Abstract: A method for encoding a picture of a video sequence in a bit stream that reduces slice header parsing overhead is provided. The method includes determining weighting factors that may be used for weighted prediction in encoding at least one slice of the picture, wherein a total number of the weighting factors is constrained to not exceed a predetermined threshold number of weighting factors, wherein the threshold number is less than a maximum possible number of weighting factors, and signaling weighted prediction parameters including the weighting factors in a slice header in the bit stream.

Abstract: A saw blade for dicing a sheet of copper alloy to form individual resistors is disclosed, wherein the sheet of copper alloy has a thickness of less than 0.3 mm. The saw blade includes a ring having a first side, a second side, and a circumferential surface, wherein the thickness of the ring between the first side and the second side is less than 0.6 mm.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.

Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.