Abstract: A method is provided. A first reference voltage during an idle mode is selected, and the first reference voltage is applied to a switched-mode converter. A first output voltage is then generated by the switched-mode converter from a power supply, and a capacitor is overcharged with the first output voltage. The first output voltage is regulated to generate a second output voltage during the idle mode. Then, a second reference voltage during a quiet mode, where the second reference voltage to the buck converter. During the quiet mode, a third output voltage is generated from the switched-mode converter and from discharging the overcharged capacitor, and the third output voltage is regulated to generate the second output voltage.

Abstract: A segmented digital-to-analog converter (DAC) circuit includes an interpolation resistor DAC (RDAC) and a buffer amplifier. The interpolation RDAC includes a resistor-two-resistor (R-2R) DAC and a resistor ladder. The R-2R DAC is configured to receive a first subword and generate an analog output signal with a voltage representative of the first subword. The first subword has an integer number M bits that include a most significant bit (MSB) of a digital input signal. The resistor ladder is configured to receive the analog output signal and a second subword and generate an analog interpolated signal. The second subword has an integer number I bits that include an intermediate significant bit (ISB) of the digital input signal The buffer amplifier is configured to receive the analog interpolated signal and generate an output signal for the segmented DAC.

Abstract: An integrated AMR angular sensor includes a first sensor resistor and a second sensor resistor. The first sensor resistor and the second sensor resistor each has a plurality of magnetoresistive segments containing magnetoresistive material that are electrically coupled in series. The magnetoresistive segments of each sensor resistor are parallel/anti-parallel to each other. The magnetoresistive segments of the second sensor resistor are perpendicular to the magnetoresistive segments of the first sensor resistor. The first magnetoresistive segments are divided into a first group and a second group, which are disposed in a balanced distribution relative to a sensor central point of the integrated AMR angular sensor. Similarly, the second magnetoresistive segments are divided into a first group and a second group, which are disposed in a balanced distribution relative to the sensor central point.

Abstract: A light emitting diode system allows for high current end user LED matrix applications while mitigating internal damage to control circuitry that may be caused by excess current flow. In one example, multiple switches operate in parallel across an LED. When an overvoltage condition is detected in a first switch, a logic circuit determines those switches programmed to operate in parallel and causes them to conduct current. This reduces the amount of current flowing through any one switch and mitigates harm to the device. The parallel configuration of switches may be driven by a single pulse width modulated current. This allows the drive current to be divided between parallel transistors, limiting the damaging effects that can be caused by high currents flowing through the transistors.

Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

Abstract: Circuits and methods for testing wafers are disclosed herein. An embodiment of a method includes electrically contacting a first probe and a second probe to a wafer. A gas is blown in the areas proximate the first probe and the second probe. An electric potential is then applied between the first probe and the second probe while the gas is being blown.

Abstract: A sensor cell has a chamber that defines an internal sensor volume for a sensor fluid in a vapor phase. A signal path extends into the internal sensor volume. The sensor cell includes a condensation reservoir for a condensed phase of the sensor fluid, in fluid communication with the internal sensor volume. The signal path is spatially separate from the condensation reservoir. During operation of the sensor cell, some of the sensor fluid may be converted to a vapor phase in the internal sensor volume. During such operation, sensor fluid in the condensed phase is disposed in the condensation reservoir, advantageously out of the signal path, leaving the signal path desirably free of the condensed phase sensor fluid. During periods of non-operation, a significant portion of the sensor fluid may condense from the vapor phase to the condensed phase in the condensation reservoir, advantageously out of the signal path.

Abstract: A DCDC converter includes a transconductance amplifier, a comparator, a current driving component, an output impedance, a switch, a clamp resistor and a p-channel FET. The transconductance amplifier outputs a transconductance current and a switch control signal. The comparator has a two n-channel FET inputs forming a differential pair and outputs a compared signal. The current driving component generates an output current based on the compared signal. The output impedance component generates an output DC voltage based on the output current. The switch is between the two n-channel FETs and can open and close based on the switch control signal. The clamp resistor is arranged in series with the switch. The p-channel FET is in series with the clamp resistor and is controlled by the output DC voltage.

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

Abstract: In accordance with at least one embodiment of the disclosure, a method of patterning platinum on a substrate is disclosed. In an embodiment, an adhesive layer is deposited over the substrate, a sacrificial layer is deposited over the adhesive layer, and a patterned photoresist layer is formed over the sacrificial layer. Then, the sacrificial layer is patterned utilizing the photoresist layer as a mask such that at least a portion of the adhesive layer is exposed. Subsequently, the top and sidewall surfaces of the patterned sacrificial layer and the first portion of the adhesive layer are covered by a platinum layer. Finally, the sacrificial layer and a portion of the platinum layer covering the top and sidewall surfaces of the sacrificial layer are etched, thereby leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate.

Abstract: A control unit, in a disclosed embodiment, includes a transceiver, memory, and a processor. The processor is coupled to the transceiver and memory and executes instructions from the memory to cause the control unit to receive a first transmission containing a certificate, verify the authenticity of the certificate, and, after verifying authenticity of the certificate, execute a public key agreement protocol to generate a first common secret encryption key, receive a second transmission containing an encrypted first public key that is encrypted by the first common secret encryption key, decrypt the encrypted first public key using the first common secret encryption key to determine the first public key, execute a public key agreement protocol to generate a second common secret encryption key, generate an operational key, encrypt the operational key using the second common secret encryption key, and transmit the encrypted operational key.

Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.

Abstract: An embodiment includes a method and an encoder for SSIM-based bits allocation. The encoder includes a memory and a processor utilized for allocating bits based on SSIM, wherein the processor estimates the model parameter of SSIM-based distortion model for the current picture and determines allocates bits based on the SSIM estimation.

Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

Abstract: A method and apparatus for sample adaptive offset without sign coding. The method includes selecting an edge offset type for at least a portion of an image, classifying at least one pixel of at least the portion of the image into edge shape category, calculating an offset of the pixel, determining the offset is larger or smaller than a predetermined threshold, changing a sign of the offset based on the threshold determination; and performing entropy coding accounting for the sign of the offset and the value of the offset.

Abstract: For inductive sensing (such as for proximity switching), differential inductance readout is based on Sense/Reference resonators implemented as LC-ring oscillators, with LS/LR inductor coils and a shared (time-multiplexed) resonator capacitor. The ring oscillators include matched Lsense/Lref drivers time-multiplexed (by out enable signals), to provide Lsense/Lref resonator excitation signals to the Lsense/Lref resonators, based on resulting Lsense/Lref resonance measurements (such as of resonance state) acquired by the ring oscillators from the Lsense/Lref resonators. Differential readout data is based on the time-multiplexed Lsense/Lref resonance measurements, corresponding respectively to LS/LR coil inductances (such as based on Lsense/Lref resonator oscillation frequency). The ring oscillators can be implemented with a Schmitt trigger, converting analog resonance measurements into digital input to the Lsense/Lref drivers. Driver matching and layout matching can be used to improve accuracy.

Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

Abstract: A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.

Abstract: A method of regenerative braking includes providing an electric motor including at least one stator and a rotor, a speed of the rotor, a motor controller that regulates a current level in the stator winding, a power inverter which controls an energy flow to the stator terminal, and an energy storage system (ESS) which exchanges energy with the motor. A battery management circuit is between the power inverter and the ESS, and a processor has an associated memory storing a regenerative braking (RB) algorithm. The RB algorithm during braking causes the motor controller to execute determining an RB torque value from the rotor speed that maximizes regenerative braking current, and the power inverter is used to redirect the RB current to maximize a power transfer from the motor to the ESS.

Abstract: An apparatus for mapping data in a wireless communication system. The apparatus includes circuitry for generating a precoding matrix for multi-antenna transmission based on a precoding matrix indicator (PMI) feedback from at least one remote receiver where the PMI indicates a choice of precoding matrix derived from a matrix multiplication of two matrices from a first code book and a second codebook. The apparatus further includes circuitry for precoding one or more layers of a data stream with the precoding matrix and transmitting the precoded layers of data stream to the remote receiver.