Abstract: A system having a set of power amplifiers each having a primary inductive structure configured to provide an output signal. A secondary inductive structure is configured to inductively couple to each of the primary inductive structures. A transmission line is provided with a signal trace and a ground trace. The signal trace of the transmission line is connected to a first end of the secondary inductive structure. A return path from a second end of the secondary inductive structure is coupled via a resonant network to the ground trace of the transmission line, in which the return path is spaced away from the secondary inductive structure to minimize inductive coupling to the primary structures.

Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

Abstract: Described example user interface control apparatus includes a first structure, with a first side, conductive capacitor plate structures spaced along a first direction on the first side, a movable second structure with an auxiliary conductive structure, and an interface circuit to provide excitation signals to, and receive sense signals from, the conductive capacitor plate structures to perform a mutual capacitance test and a self-capacitance test of individual ones of the conductive capacitor plate structures to determine a position of the second structure or a user's finger relative to the first structure along the first direction.

Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.

Abstract: A BLE-Mesh device includes a controller, an RF driver for driving the transceiver adapted to be coupled to an antenna, and a counter. The controller implements an applications layer including BLE and Mesh Applications, and a BLE stack and a mesh stack. A redundant traffic suppression relaying algorithm is for waiting for a random time within a selected time window from W1 to a later W2 before attempting to transmit a first packet that contains a unique source (SRC) address and a packet sequence (SEQ) number of a device that is the source of the first packet. If during the random time a packet with both the source device's SRC address and the SEQ number is received, the counter is incremented from an initial count to a current count. After the random time elapses, the current count is compared to a Cthreshold value, and the first packet is transmitted only if the current count<the Cthreshold value.

Abstract: A power supply, comprising a controller comprising a first switch coupled between a first node and a second node, a first resistor coupled between the second node and a third node, a second resistor coupled between the first node and a fourth node, a capacitor coupled between the fourth node and a fifth node, an amplifier coupled at a first input to the fourth node, at a second input to the third node, and at an output to the fifth node, and a comparator coupled at a first input to the fifth node and at a second input to the third node.

Abstract: A circuit and apparatus for filtering harmful harmonics is disclosed. The circuit and apparatus include a power amplifier core that uses equally sized inverter based amplifiers. The amplifier core cells provide uniform load to all phases of a fundamental frequency to cancel all harmonics at an output. The power amplifier stages are driven into nonlinearity, and the combination of harmonics is performed at the output by varying series connected capacitors. The harmonic combination is performed at the output, leaving no further scope of nonlinearity in the signal chain.

Abstract: A resonant impedance sensing system includes a class D negative impedance stage implemented with a Class D comparator, and a loop control stage implemented with an output comparator clocked by the class D comparator, establishing a negative impedance control loop that includes the resonator as a loop filter. The negative impedance stage includes a multi-level current source (such as a current DAC) interfaced to the resonator through an H-bridge controlled by the class D comparator. Class D switching synchronizes resonator oscillation voltage (input to the class D comparator) with resonator current drive (from the multi-level current source), driving the resonator with a negative impedance that balances resonator impedance to maintain sustained oscillation.

Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.

Abstract: In at least some embodiments, a communication device includes a transceiver with a physical (PHY) layer. The PHY layer is configured for body area network (BAN) operations in a limited multipath environment using M-ary PSK, differential M-ary PSK or rotated differential M-ary PSK. Also, the PHY layer uses a constant symbol rate for BAN packet transmissions.

Abstract: A voltage regulator includes an output transistor, an error amplifier coupled to the output transistor, a cascode transistor coupled to the output transistor in series, and a cascode bias circuit coupled to the cascode transistor and the output transistor. The output transistor is configured to generate an output signal at a first voltage. The error amplifier is configured to receive a reference signal. The cascode bias circuit is configured to bias the cascode transistor such that, in response to a drain-to-source short circuit of the output transistor, the cascode transistor generates the output signal at the first voltage.

Abstract: Disclosed examples include isolated dual active bridge (DAB) DC to DC converters with first and second bridge circuits, a transformer with a sense coil, and a secondary side control circuit to provide secondary side switching control signals to regulate an output voltage or current signal by controlling a phase shift angle between switching transitions of the secondary side switching control signals and switching transitions of a secondary side clock signal, where the secondary side control circuit includes a clock recovery circuit to synchronize the secondary side clock signal to transitions in a sense coil voltage signal of the sense coil.

Abstract: A driver circuit includes a first termination resistor and a distributed amplifier comprising a plurality of pairs of input transistors and comprising inductors coupled between each pair of input transistors. The driver circuit also includes a distributed current-mode level shifter coupled to the first termination resistor. The distributed current-mode level shifter includes a first plurality of inductors coupled in series between the first termination resistor and the distributed amplifier and a first plurality of capacitive devices. Each capacitive device is coupled to a power supply node and to a node interconnecting two of the series-coupled inductors.

Abstract: Remote sensors and methods of remote sensing are disclosed. A remote sensor includes a first circuit and a second circuit. The first circuit includes a first coil, a magnetic field generator for driving a current through the first coil to generate a magnetic field, and circuitry for determining loading of the magnetic field. The second circuit includes a second coil located proximate the first coil and a voltage-to-current converter for converting a voltage at an input of the second circuit to current and applying the current to the second coil. The current in the second coil registers as a loading of the magnetic field generated by the first coil. The loss, in response to the loading of the magnetic field, is measurable by the first circuit.

Abstract: An isolated insulated gate bipolar transistor (IGBT) gate driver is provided which integrates circuits, in-module, to support the measurements of threshold voltage, and collector-emitter saturation voltage of IGBTs. The measured gate threshold and collector-emitter saturation voltage can be used as precursors for state of health predictions for IGBTs. During the measurements, IGBTs are biased under specific conditions chosen to quickly elicit collector-emitter saturation and gate threshold information. Integrated analog-to-digital converter (ADC) circuits are used to convert measured analog signals to a digital format. The digitalized signals are transferred to a micro controller unit (MCU) for further processing through serial peripheral interface (SPI) circuits.

Abstract: In operation of a flybuck converter, a first output capacitor is charged and, after this charging, charge is transferred from the first output capacitor to a second output capacitor. The charge transferring includes closing a switch to establish a first current path through which the first output capacitor discharges current that induces, in a second current path, current that charges the second output capacitor. While the switch is closed during the charge transfer, a current limit condition in the switch is detected. In response to detection of the current limit condition, the switch is opened, and is thereafter closed again before attempting to charge the first output capacitor again, thereby to resume transferring charge from the first output capacitor to the second output capacitor.

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.

Abstract: Optical time domain reflectometer (OTDR) systems, methods and integrated circuits are presented for locating defects in an optical cable or other optical cable, in which a first optical signal is transmitted to the cable and reflections are sampled over a first time range at a first sample rate to identify one or more suspected defect locations, and a second optical signal is transmitted and corresponding reflections are sampled over a second smaller time range at a higher second sample rate to identify at least one defect location of the optical cable for relaxed memory requirements in the OTDR system.

Abstract: A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is transmitted from a NodeB in a cell to UE within the cell. The NodeB transmits a specific SRI subframe offset and an index value to the particular UE within the cell. The specific SRI subframe offset and the index value enable the UE to determine a unique combination of cyclic shift, RS orthogonal cover, data orthogonal cover, and resource block number for the UE to use as a unique physical resource for an SRI in the physical uplink control channel (PUCCH).