Abstract: Electrophoretic displays (EPDs) and methods for controlling EPDs are disclosed herein. An embodiment of an EPD includes a first operating format, wherein pixels on at least one area of the EPD are driven individually. The EPD has a second operating format, wherein a plurality of pixels constituting at least one area of the EPD are driven simultaneously. Both the first operating format and the second operating format are performable simultaneously on the EPD.

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract: Several systems and methods for data processing are disclosed. In an embodiment, a data processing system includes a host processor, a plurality of slave processors and a plurality of frame buffers. Each slave processor is associated with at least one data co-processor configured to process data sub-frames based on one processing stage. For a first data sub-frame, a first messaging call is provisioned to the host processor by each slave processor subsequent to execution of a processing stage by an associated data co-processor. The host processor is configured to provision a second messaging call to a next slave processor upon receiving the first messaging call. Further, for each subsequent data sub-frame, a third messaging call is provisioned by each slave processor to a next slave processor subsequent to execution of the corresponding processing stage by the associated data co-processor for facilitating execution of the next processing stage.

Abstract: A MEMs actuator device and method of forming includes arrays of actuator elements. Each actuator element has a moveable top plate and a bottom plate. The top plate includes a central membrane member and a cantilever spring for movement of the central membrane member. The bottom plate consists of two RF signal lines extending under the central membrane member. A MEMs electrostatic actuator device includes a CMOS wafer, a MEMs wafer, and a ball bond assembly. Interconnections are made from a ball bond to an associated through-silicon-via (TSV) that extends through the MEMS wafer. A RF signal path includes a ball bond electrically connected through a TSV and to a horizontal feed bar and from the first horizontal feed bar vertically into each column of the array. A metal bond ring extends between the CMOS wafer and the MEMS wafer. An RF grounding loop is completed from a ground shield overlying the array to the metal bond ring, a TSV and to a ball bond.

Abstract: An integrated circuit includes a motor current input voltage-to-current (VI) converter that receives a motor current sensor voltage from a motor and a reference voltage to generate an output current related to a motor's current. A motor current calibration VI converter compensates for errors in the motor current input VI converter and generates a calibration output current based on the reference voltage, wherein the output current and the calibration output current are combined to form an estimate of the motor's current.

Abstract: Power-supply ripple rejection (PSRR) at high frequencies is improved for an LDO voltage regulator with an NMOS pass transistor (MN1). A ripple voltage (Vripple) present on the input voltage causes a ripple current (Iripple) through parasitic gate-drain capacitance of the pass transistor. A small ripple current (Ifraction) proportional to the ripple current (Iripple) is generated and amplified to generate a cancellation current (Icancel). The cancellation current is drawn from the gate of NMOS pass transistor (MN1) to cancel the ripple current so that no net ripple current flows through the finite output impedance of an error amplifier (2), to thereby achieve the PSRR improvement.

Abstract: An electronic device that includes a power on reset, a variable power supply filter coupled to the power on reset, and control logic coupled to the power on reset and the variable power supply filter. The control logic is configured to activate the variable power supply filter based on a core domain of the electronic device being active.

Abstract: System, method, and silicon chip package for providing structural strength, heat dissipation and electrical connectivity using “W” shaped frame bonded to the one or more dies, wherein the “W” shaped frame provides compression strength to the silicon chip package when the one or more dies are bonded, and electrically conductivity between for the one or more dies to leads of silicon chip package, and heat dissipation for the silicon chip package.

Abstract: A system for write-once memory (WOM) code emulation of EEPROM-type devices includes, for example, a host processor for sending data words for storing in a WOM (Write-Only Memory) device. A host interface receives the data words for encoding by a WOM controller. An emulator programs the WOM-encoded data and an address identifier as an entry of the WOM device. The emulator overwrites previously programmed WOM-encoded data by searching entries of a current active page of a WOM device to locate a programmed WOM entry that includes the searched-for address identifier and the previously written WOM-encoded data word. When the previously written WOM-encoded word cannot be correctly overwritten, the contents of the second WOM-encoded word are stored in a new entry. When the current active page is substantially full, the new entry is stored a new page and the current active page is block-erased.

Abstract: Methods and apparatus permit body biasing to be controlled for transistors of a logic device. By controlling the body biasing, transistor threshold voltages can be controlled—increased during standby modes of the logic device to reduce leakage current and decreased during active modes and to increase switching speed during the active modes. The change in the body biasing can be made relatively slowly to reduce wasted energy that would otherwise be dissipated as heat. In a method embodiment, the method includes obtaining first and second body bias slope parameters, each slope parameter defining, at least in part, a slope of a body bias voltage signal. The method includes charging a body of a transistor with a bias voltage signal per the first body bias slope parameter to lower a threshold voltage, and discharging the body per the second body bias slope parameter to decrease leakage current of the transistor.

Abstract: A method for controlling the temperature of a semiconductor device-under-test (DUT) by forming an apparatus (100) including a feedback loop between a Temperature Forcing Unit (TFU, 110) conductively tied to an Automated Test Equipment (ATE, 120) having a chamber encasing the DUT (122), and the ATE conductively connected to a Control Computer (CC, 130) conductively tied back to the TFU. The CC is calibrated with reference values of temperatures and measured voltages using a diode integral with a diode-isolated circuit protecting a pin of the DUT against electrostatic discharge. The thermal air stream to stabilize the temperature of the ATE chamber loaded with the DUT is reset by the CC until the DUT is stabilized at the goal temperature.

Abstract: Methods and devices for detecting USB devices attached to a USB charging port including a USB port having a first data line D+, a second data line D?, and a power line are disclosed. A USB device is attached to the USB port; applying power to the USB device by the power line; applying a first voltage to the line D+ at the USB port by a first impedance; applying a second voltage to the line D? at the USB port by a second impedance. The voltages on the line D+ and the line D? are then monitored at the USB port. If the voltage on the line D+ is approximately equal to a first predetermined value for a predetermined period and the voltage on the line D? is below a second predetermined value, then the USB device is determined to be of an alpha type device.

Abstract: Methods and apparatus to determine nearfield localization using phase and received signal strength indication (RSSI) diversity are disclosed. An example method includes determining a first strength of an electric field and a second strength of a magnetic field, the electric field and the magnetic field associated with an electromagnetic signal sent from a transmitter; determining a difference between the first strength and the second strength; and determining a transmitter distance based on the difference between the first strength and the second strength.

Abstract: Disclosed examples include multiple output DC to DC converters with a buck converter including a half bridge switching circuit and transformer primary winding to provide a first output voltage signal, as well as a boost converter to provide an isolated second output voltage signal. The boost converter includes a transformer secondary winding magnetically coupled with the primary winding to provide a boost converter inductor, a switching circuit, an output diode providing the second output voltage signal, and a PWM controller that synchronizes the boost converter switching with the low side switch of the buck converter based on a sensed voltage of the transformer secondary winding.

Abstract: A first apparatus includes a vapor cell having first and second cavities fluidly connected by multiple channels. The first cavity is configured to receive a material able to dissociate into one or more gases that are contained within the vapor cell. The second cavity is configured to receive the one or more gases. The vapor cell is configured to allow radiation to pass through the second cavity. A second apparatus includes a vapor cell having a first wafer with first and second cavities and a second wafer with one or more channels fluidly connecting the cavities. The first cavity is configured to receive a material able to dissociate into one or more gases that are contained within the vapor cell. The second cavity is configured to receive the one or more gases. The vapor cell is configured to allow radiation to pass through the second cavity.

Abstract: A circuit and method for memory characterization. The circuit includes first and second programmable delay lines, address and data registers, an output register and a finite state machine controller. The finite state machine controller supplies an address to the address register, data to the data register and controlling a delay of the first programmable delay line and the second programmable delay line in at least one predetermined sequence to determine an operating characteristic of the memory to be tested. The programmable delay lines may be connected as a ring oscillator. Determination of the frequency of the ring oscillator via a counter determines the delay of the delay line. The programmable delay lines, the address register and data registers, the output register, the finite state machine controller and the memory to be tested are preferably constructed on a same semiconductor substrate.

Abstract: An electronic system comprising an electronic body (301) with terminal pads (310) and at least one capacitor embedded in the electronic body. The capacitor including an insulating and adhesive first polymeric film (302) covering the body surface except the terminal pads; a sheet (320) of high-density capacitive elements, the first capacitor terminal being a metal foil (321) attached to film (302), the second terminal a conductive polymeric compound (324), and the insulator a dielectric skin (323). Sheet (320) has sets of via holes: the first set holes reaching metal foil 321), the second set holes reaching the terminals (310), and the third set holes reaching the conductive polymeric compound (324). An insulating second polymeric film (303) lining the sidewalls of the holes and planarizing the sheet surface; and metal (432) filling the via holes between the polymeric sidewalls and forming conductive traces and attachment pads on the system surface.

Abstract: An instrumentation amplifier (INA) that includes a first amplifier and a second amplifier coupled to the first amplifier. The first amplifier includes a first transistor. The first amplifier is configured to receive a positive phase signal of a differential signal. The second amplifier includes a second transistor and is configured to receive a negative phase signal of the differential signal. The first and second transistors each include a gate, source, and drain. The first transistor drain is connected to the second transistor drain.

Abstract: A method and apparatus for encoding bit code utilizing context dependency simplification to reduce dependent scans. The method includes retrieving at least one 2 dimensional array of transform coefficient, transforming the at least one 2 dimensional array of transform coefficient to a 1 dimensional coefficient scanning using a diagonal scan in a fixed direction, utilizing the at least one 1 dimensional array of transform coefficients for context selection based on fewer than 11 neighbors, potentially selected based on scan direction, slice type, coding unit type and binarization, and performing arithmetic coding to generate coded bit utilizing context selection and binarization.

Abstract: Several systems and methods for accessing files stored in a storage device are disclosed. In an embodiment, the method includes accessing a file allocation table (FAT) in a computer file system associated with the storage device. The FAT includes a plurality of cluster addresses corresponding to a plurality of clusters allocated to a file stored in the storage device. A cluster address is read to identify a location of a next cluster. One or more bits in the cluster address are read to determine a presence of a signature value indicating allocation of a set of contiguous clusters from among the plurality of clusters. A number of contiguous clusters is computed based on a pre-determined number of consecutive cluster addresses succeeding the cluster address if the signature value is present. The set of contiguous clusters are read from the storage device based on the computed number of contiguous clusters.