Abstract: An imaging device capable of capturing depth information or surface profiles of objects is disclosed herein. The imaging device uses an enclosed flashing unit to project a sequence of structured light patterns onto an object and captures the light patterns reflected from the surfaces of the object by using an image sensor that is enclosed in the imaging device. The imaging device is capable of capturing an image of an object such that the captured image is comprised of one or more color components of a two-dimensional image of the object and a depth component that specifies the depth information of the object.

Abstract: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a preamplifier circuit, a latch circuit and a current re-use circuit. The current re-use circuit applies a current to the preamplifier circuit during a transparent phase, and applies a similar current to the latch circuit during a latch phase.

Abstract: One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed.

Abstract: An example disclosed method to handle a reference voltage change in a digital power supply includes receiving a first value associated with a first reference voltage having a first voltage magnitude at a digital signal processor of a digital power supply, comparing the first reference voltage to an output voltage of the digital power supply, controlling the digital power supply based on the comparison between the first reference voltage and the output voltage, receiving a second value associated with a second reference voltage having a second voltage magnitude, determining that the first voltage magnitude is different than the second voltage magnitude, in response to determining that the second voltage magnitude is different than the first voltage magnitude, determining a voltage profile, and controlling the digital power supply based on the voltage profile.

Abstract: A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.

Abstract: The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion (510) of a substrate (220) to a first etch process, the first etch process designed to etch at a first entry angle (?1), and subjecting a second portion (610) of the substrate (220) to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (?2).

Abstract: A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.

Abstract: A CMOS output driver is provided for driving a capacitive load over a circuit trace in high speed applications. The CMOS output driver comprises a signal input and a signal output. The output driver has a first buffer amplifier with an input connected to the signal input and an output connected to the signal output through a resistor. A second buffer amplifier is also provided, which has an input connected to the signal input and an output connected to the signal output through a capacitor.

Abstract: A polyphase electric energy meter is provided that includes a microcontroller with a front end that converts analog current input signals and analog voltage input signals to digital current and voltage samples for processing by the microcontroller. The front end includes separate input channels, each for one of the current input signals with a sigma-delta modulator followed by a decimation filter. The front end further includes a common input channel for all voltage input signals with a multiplexer, an analog-to-digital converter and a de-multiplexer. The separate input channels and the common input channel provide the digital current and voltage samples for processing by the microcontroller.

Abstract: An improved compensation circuit that compensates for lifetime performance drifts due to aging of integrated circuits to improve the circuit performance. In one example embodiment, this is achieved by applying a body bias voltage VBB to the integrated circuit to compensate for the lifetime performance drift due to hot carrier and NBTI induced aging.

Abstract: Disclosed embodiments reveal techniques for efficiently allocating time slots in a time-division multiplex (TDM) cycle among multiple channels of varying size, particularly when the channels do not all desire an integer number of time slots. TDM cycles can only allocate an integer number of time slots to each channel. So when at least one channel does not desire an integer number of time slots, then the disclosed embodiments allocate a number of time slots equal to the integer portion to each channel, rolling any fractional remainder over to the next cycle. This cumulative cyclical fractional summing process efficiently allocates time slots among the channels, allowing the average allocation per cycle to approach the true non-integer desired amount over time.

Abstract: A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.

Abstract: In one embodiment, the transmitter is for use with a cellular communication network and includes an offset determination unit configured to select a shift parameter for a channel quality indication, wherein the shift parameter corresponds to an adjustment in an energy per resource element ratio for reporting the channel quality indication. The transmitter also includes a sending unit configured to signal the shift parameter. In another embodiment, a receiver is for use with a cellular communication network and includes a reception unit that receives a transmission. The receiver also includes an offset interpretation unit configured to interpret a shift parameter for a channel quality indication from the transmission, wherein the shift parameter corresponds to an adjustment in an energy per resource element ratio for reporting the channel quality indication.

Abstract: A mode-switching network transmitter is for use with a network MIMO super cell and includes a super cell control unit configured to orchestrate a transmission from the network MIMO super cell, wherein the transmission is supplied from a portion of super cell transmission points. The mode-switching network transmitter also includes a transmission unit configured to provide the transmission. Additionally, a transmission mode-switching receiver is for use with user equipment in a network MIMO super cell and includes a reception unit configured to receive a transmission for the user equipment within the network MIMO super cell. The transmission mode-switching receiver also includes a processing unit configured to process the transmission, wherein the transmission is supplied from a portion of super cell transmission points.

Abstract: An apparatus, a method of transmitting data having audio and video content over a broadcast network employing time-slicing, a DVB-H system and an audio and video data processor. In one embodiment the method includes: (1) identifying points of a data stream corresponding to a beginning of each time-slice of a transmission stream, having multiple time-slices, to be used to transmit the data stream via a broadcast network, the data stream including an audio and a video stream, (2) injecting a synchronization packet at the points for each of the audio and video streams and (3) transmitting the transmission stream having the synchronization packets via the broadcast network.

Abstract: A semiconductor PoP device (100) includes a first device (101) with a first substrate (110) having on its first side (110a) a stack (115) of at least two chips, first contact pads (111), and a first package (116) having a height (116a) and a top surface (116b). Via holes (130) extend from the top package surface through the package height to the first contact pads; the vias have straight sidewalls and a diameter at the top surface of less than 75% of the height. The PoP further includes a second packaged device (102) with a second substrate (120) facing the top surface (116b) of the first package; substrate (120) has contact pads (121) in line with the first pads (111). Solder bodies (103) fill the vias (130) and connect the pads (121) with the respective first pads (111).

Abstract: A frequency synthesizer and a method of synthesizing an output signal. In one embodiment, the frequency synthesizer includes: (1) a substrate, (2) a resonator located on the substrate and comprising a micro electromechanical system device and a feedback amplifier coupled thereto, (3) a phase-locked loop located on the substrate and coupled to the resonator, (4) control logic located on the substrate and configured to control the phase-locked loop based on a known resonant frequency of the micro electromechanical system device and (5) a voltage-controlled oscillator located on the substrate and coupled to the phase-locked loop.

Abstract: In accordance with the teachings of the present disclosure, a system and method for displaying an image are provided. In one embodiment, the method includes receiving a data stream representing a frame of an image. The data stream may indicate a first color pixel cluster corresponding to a first color and a second color pixel cluster corresponding to a second color. The first color pixel cluster and the second color pixel cluster may be displayed. The first color pixel cluster may be different from the second color pixel cluster.

Abstract: A frequency divider (10A) includes an asynchronous finite state machine (AFSM) configured as a counter (20) having an input coupled to an input clock signal (CLK) for producing information representative of a plurality of phase signals (F0,F1,F2,F3) each of which is a divided-down representation of the input clock signal (CLK) and each of which is phase-shifted by a predetermined amount with respect to another of the phase signals (F0,F1,F2,F3). Programmable circuitry (22) operates in response to both dynamic divide ratio information (DIV_RATIO) and the information representative of the plurality of phase signals (F0,F1,F2,F3) so as to generate an output clock signal (CLKOUT) that is divided down according to both the dynamic divide ratio information and the information representative of the plurality of phase signals (F0,F1,F2,F3).

Abstract: In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.