Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

Abstract: Methods, apparatus, and articles of manufacture are disclosed for removing an undesired component from a low intermediate frequency signal having an intermediate center frequency and an undesired component at a first frequency. One example method may include determining an amplitude of the undesired component; frequency shifting the low intermediate frequency signal from the intermediate center frequency to produce a zero intermediate frequency signal; filtering the zero intermediate frequency signal; generating a tone based on the amplitude of the undesired component; and subtracting the tone from the filtered zero intermediate frequency signal to remove the undesired component.

Abstract: A raised solder-mask-defined (SMD) pad configured for receiving a solder ball on a laminate electronic circuit board and a method of creating the raised SMD pad on a laminate electronic circuit board. The method may comprise forming a base bump, covering the base bump with a conductive bump layer and layering a surrounding material over an extended edge of the conductive bump layer. The surrounding material is patterned to expose a pad face and of a portion of the sides of the conductive bump layer, such that the pad face is disposed above the surface of the surrounding material. The surrounding material may be patterned by a photolithography operation or alternatively, a laser-drill operation.

Abstract: A device for receiving a RF signal over multiple channels, a receiver incorporating the device, a method of providing digital calibration values for a digitally-tunable resonant circuit of the device, and a method of processing an RF signal. In one embodiment the device includes: (1) a low-noise amplifier having a digitally-tunable resonant circuit, (2) a memory configured to store digital calibration values particular to the device and (3) a time-constant controller coupled to the low-noise amplifier and configured to retrieve from the memory at least one of the digital calibration values as a function of a channel to be received and, based on the at least one, to cause the digitally-tunable resonant circuit to provide a time-constant corresponding to the channel to be received.

Abstract: Methods and systems are disclosed for forming secure wirebonds between electrical contacts in electronic device assemblies. Representative embodiments of the invention are described for forming a wirebond including system components and method steps for generating electromagnetic energy from a heat source and transmitting heat to a ball formed on a bondwire. Subsequently, pressure applied to the ball at the bonding site is used in the formation of a wirebond.

Abstract: A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to a signal input and a tunable filter. The tunable filter comprises an input stage with a first pair of inductors arranged in a dipole configuration and a second tunable capacitor coupled in parallel to the first pair of inductors and an output stage inductively coupled to the input stage, the output stage includes a second pair of inductors also arranged in a dipole configuration and a third tunable capacitor coupled in parallel to the second pair of inductors. The inductors are realized using bond wire or any other high Q material. The first tunable capacitor, the second tunable capacitor, and the third tunable capacitor can be tuned using a master-slave tuning configuration to adjust the operating frequency of the amplifier and the tunable filter to enable frequency band compatibility with multiple communications protocols.

Abstract: Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The exemplary triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.

Abstract: In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.

Abstract: A method of forming a MEMS structure over active circuitry in a semiconductor body includes forming active circuitry in a semiconductor body, and forming the MEMS structure over the active circuitry, wherein at least a portion of the MEMS structure spatially overlaps the active circuitry.

Abstract: An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15th digit to the 16th digit in the result of addition from the 1st digit to the 16th digit of the input data is generated on the basis of bit signals (a0-a15, b0-b15) for the portion from the 1st digit to the 15th digit of the input data, and of carry signal CIN input to the 1st digit, and it is output from CLA 204. Then, carry signal c15 from the 16th digit to the 17th digit is generated based on said generated carry signal c14 and bit signals (a15, b15) of the 16th digit of the input data, and this is output from CIA 205. Exclusive-NOR circuit 206 then operates on said carry signals c14 and c15, and overflow detection signal OVF16 is generated.

Abstract: A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to manage memory access by the DSP, and the DSP and the microprocessor access shared physical memory. Upon the DSP executing an instruction attempting to access a virtual address wherein the virtual address is invalid, a page fault interrupt is generated by the DSP MMU. A microprocessor interrupt handler in the microprocessor is activated in direct response to the page fault interrupt. Thereafter in the microprocessor, a translation lookaside buffer (“TLB”) entry is created in the DSP MMU, which includes a valid mapping between the virtual address and a page of physical memory. After creating the TLB entry, the microprocessor indicates to the DSP that the access by the DSP of the virtual address is completed.

Abstract: One embodiment of the invention includes a differential amplifier circuit. A first input stage generates first and second control voltages in response to a differential input signal. A second input stage generates third and fourth control voltages in response to the differential input signal. The first and second control voltages can be inversely proportional and the third and fourth control voltages can be inversely proportional. The circuit also includes a first output stage that is configured to set a magnitude of a first output voltage of a differential output signal at a first output node in response to the first and second control voltages. The circuit further includes a second output stage that is configured to set a magnitude of a second output voltage of the differential output signal at a second output node in response to the third and fourth control voltages.

Abstract: An arrangement avoids contention on a communication medium among devices including at least a transmitter and a receiver. The arrangement involves a first portion configured to instruct a receiver to indicate that the communication medium is busy for a time period substantially longer than an actual frame transmission period being sent from the transmitter to the receiver, and a second portion configured to prohibit the receiver from transmitting on the communication medium during the time period.

Abstract: Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm?2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

Abstract: During trace recording, on-chip trace export mechanisms may schedule output from multiple sources out of order of execution. This makes the exact arrival of trace information in the receiver imprecise. Time of the day or time stamp information may be placed in the trace stream itself to assure correct timing, and represented as a control word. This may be done periodically or at the first empty slot after some period has elapsed.

Abstract: A circuit arrangement and method for improving load regulation in an amplifier (e.g., LDO amplifier) uses a feedback circuit including a parallely connected feedback resistance Rf and a noise reduction feedback capacitance Cf, wherein an external capacitance has equivalent series resistance (ESR). The circuit arrangement includes a resistance Resr in the amplifier output, a junction point of the feedback resistance Rf and the feedback capacitor Cf being connected to a negative input of the LDO amplifier. Additionally, the circuit arrangement might include a resistance Rintentional in between Cf and Rf. The circuit arrangement provides good load regulation and better stability without increase in power/area. The arrangement supports external feedback mode providing design flexibility without compromising amplifier-stability, which provides high output current drive capability or enables driving heavy output capacitance.

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract: A narrow scanning aperture, lens, and mirror are added to a digital camera to enable image or text scanning. A motion sensor on the same face as the scanner aperture provides approximate scan speed data as the scanner aperture is pressed against and manually moved across the document being scanned. Many documents are too large to scan in one strip, in which case multiple strips are scanned. As each strip is scanned, a bit-mapped image of the strip is created in a data buffer. Data from each strip is passed to a final image RAM which, on completion of scanning, holds a bit-mapped image of the entire scanned page, in B/W, gray scale, or color. Multi pass strip align then processes the image data to remove redundant data (from strip overlap) and position skew (from errors in position during the scan), resulting in a more accurate bit-mapped image in final image RAM of the entire scanned page or item. Image compression compresses the bit-mapped image to standard JPEG format for storage on the camera memory card.

Abstract: A technique is provided for implementing adaptive thresholds associated with HS-SCCH detection schemes; and when applied to any HS-SCCH detection scheme, the resulting false alarm probability curves are more robust to amplitude variations of the different shared control channels. The technique has low computational complexity and low storage requirements for the estimator. Such lower complexity detection schemes have been found to outperform more complex schemes when adaptive thresholds are applied.

Abstract: A transmitter is for use with a cellular communication network and includes a beamforming generation unit configured to generate a downlink beamforming transmission corresponding to multiple-layer spatial multiplexing and based on a dedicated reference signal pattern. Additionally, the transmitter also includes a transmit unit configured to transmit the downlink beamforming transmission. A receiver is for use with a cellular communication network and includes a receive unit configured to receive a downlink beamforming transmission, and a beamforming processing unit configured to process the downlink beamforming transmission corresponding to multiple-layer spatial multiplexing and based on a dedicated reference signal pattern.