Abstract: A power conversion system includes a power transfer estimator that is operable to provide a determination of the cumulative amount of power transferred through the power supply, without additional sensing elements and at extremely low power levels, and to provide such determinations periodically over potentially long periods of time commensurate with the lifetime of a limited power source such as a battery. In a power conversion system operating in a discontinuous conduction mode (DCM), the power transfer estimator determines the charge transferred during each switching cycle, and the total number of switching cycles, to calculate the cumulative amount of power transferred. The power transfer estimator is optionally operable to calculate a value for the inductance to be used in the determination of the cumulative amount of power transferred through the power supply.

Abstract: Circuitry for providing an oscillating output signal. This circuitry includes a transconductance circuit having a first input, a second input, an output. The transconductance also includes a first transistor, a second transistor, and chopping circuitry. The chopping circuitry is for alternatively connecting, in a first clock cycle phase, a first node to a first terminal of the first transistor and a second node to a first terminal of the second transistor and, in a second clock cycle phase, following the first clock cycle phase, the first node to the first terminal of the second transistor and the second node to a first terminal of the first transistor. An oscillator circuit is also included and coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

Abstract: A program optimizer includes an energy tracking system, an energy monitoring system, and a code generation control system. The energy tracking system measures a pulse signal of a DC-DC converter that provides energy to a processor. The energy monitoring system determines, based on values received from the energy tracking system, attributes of operation of the processor. The code generation control system determines whether the values indicate that the execution of a first version of a program uses an amount of energy that is outside a predefined energy range, and to: 1) identify a parameter of an instruction generator that if changed will cause a second version of the program, when to use an amount of energy that is within the predefined energy range; 2) change a value of the identified first parameter; and 3) produce a second version of the program based on the changed value of the first parameter.

Abstract: A method of singulating a wafer starts with fracturing the wafer. The method may also include attaching the dicing tape sheet to a ring frame; relatively raising a portion of the dicing tape sheet supporting the wafer with respect to the ring frame; and attaching support tape to the ring frame and the dicing tape sheet.

Abstract: A power supply system has a leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.

Abstract: A CRC (cyclic redundancy check) generator circuit (28) generates a first CRC code based on a message. The CRC code is amended to the message, creating a first data packet. Circuitry transforms the first data packet to a second data packet for suitable transmission. Digital receiver circuitry receives the second data packet. A CRC verification circuit compares a received digital CRC code portion of the second data packet to a calculated digital CRC code portion. A message is presented for processing if no error is detected. A CRC-based FEC (forward error correction) circuit receives the message and calculates a digital CRC code from the verification circuit. When an error is detected, the detected error, based on a determination of whether the detected error affects an even number of bits or an odd number of bits, is corrected.

Abstract: A method for touch detection performed by a touch processor in an optical touch detection system is provided that includes receiving an image of an illuminated surface included in the optical touch detection system, wherein the image is captured by a camera included in the optical touch detection system, subtracting a background model from the image to generate a mean-subtracted image, identifying a set of candidate touch locations in the mean-subtracted image, classifying the candidate touch locations in the set of candidate touch locations to generate a set of validated candidate touch locations, and outputting a set of final touch locations determined from the set of validated candidate touch locations.

Abstract: An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.

Abstract: A loop-powered transmitter includes a data isolation transformer including primary and secondary windings and an analog-to-digital converter (ADC) to convert a sensor signal to a digital value. The transmitter also includes a first microcontroller coupled between a multi-signal interface of the ADC and only one tap of the primary winding of the data isolation transformer, and a second microcontroller coupled to the secondary winding of the data isolation transformer. The first microcontroller is configured to receive the digital value from the ADC over the multi-signal interface and to provide data indicative of the digital value via a single output data line through the tap of the primary winding of the data isolation transformer to the second microcontroller. Unipolar voltage converters may also be included in the transmitter along with a current limiting resistor for the data isolation transformer to reduce the risk of saturating the data isolation transformer.

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract: A method for filler insertions in a circuit layout having a cell row of standard cells and gaps between the standard cells is disclosed. First, a set of filler classes, each filler class having a set of filler cells, is classified that are configured to fill the gaps depending on a design requirement. Then, a filler insertion pattern based on a required ratio is identified such that horizontal and vertical density of the set of filler classes in the circuit layout are as per the required ratio and the cell row of the circuit layout has at least one filler cell from each of the set of filler classes.

Abstract: A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.

Abstract: The present disclosure describes a low-power, low-phase-noise (LPLPN) oscillator. The LPLPN oscillator includes a resonator load, an amplifier stage, and a loop gain control circuit. The resonator load is structured to resonate at a primary resonant frequency. The amplifier stage is coupled with the resonator load to develop a loop gain that peaks at the primary resonant frequency. The loop gain control circuit is coupled with the amplifier stage, and it is structured to regulate the loop gain for facilitating the amplifier stage to generate an oscillation signal at the primary resonant frequency and suppress a noise signal at a parasitic parallel resonant frequency (PPRF).

Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

Abstract: A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.

Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

Abstract: Several methods and systems for encoding pictures are disclosed. In an embodiment, a method comprises dividing an LCU of a picture into a plurality of MERs having size equal to or less than a predetermined size. For one or more MERs of the plurality of MERs, a number of first motion searches are performed for determining a first quad-tree based on a cost function associated with a first plurality of PUs of the one or more MERs. A number of second motion searches are performed for the LCU, for determining a second quad-tree, based on the cost function associated with a second plurality of PUs of the LCU. The first quad-tree or the second quad-tree is selected for performing encoding of the picture based on a comparison of a first cost of the first quad-tree with a second cost of the second quad-tree.

Abstract: A circuit and method for providing a current limiting feature in a low dropout (“LDO”) linear voltage regulator. A pass element generates an output voltage that is less than the input voltage. The pass element is normally enabled by an error amplifier that compares a feedback signal from the output of the pass element with a reference signal. However, the pass element may be enabled by a current limiting circuit that bypasses the error amplifier to limit the current generated at the output of the pass element.

Abstract: Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.