Abstract: On the secondary side of a flyback switching power converter, a compensation diode and a voltage divider with an averaging circuit generate an output current-compensated reference voltage that is proportional to converter output current. The current-compensated reference voltage is added to a regulation feedback controller reference voltage, which in turn adjusts the negative feedback signal to the PWM regulation controller on the primary side in proportion to the converter output current draw. The net effect is to increase the converter output voltage set-point in proportion to the converter output current draw as compensation for a voltage drop in a cable connecting the converter to a powered device. More precisely-regulated voltage levels may be delivered to an input of the powered device as a result.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: In a power converter, a circuit determines an average value of an inaccessible current from an average value of an accessible current and a value of the operating duty cycle of the converter. A method of measuring an average value of an inaccessible current from a measured value of a current in a power converter by a duty cycle of a pulse width modulation (PWM) signal representing a duty cycle of the power converter. Coupling a voltage representing the measured value to an input of a low pass filter during a time period (D) and coupling the input of the low pass filter to a reference voltage during a time period (1?D).

Abstract: Disclosed examples include high-efficiency integrated circuits and inductive capacitive DC-DC converters with a first converter stage including first and second switches and an inductor, and a second converter stage including third and fourth switches and a flying capacitor. A dual mode control circuit regulates output voltage signal in a first mode when the output voltage signal is below a threshold by pulse width modulating the switches of the first converter stage. When the output voltage exceeds the threshold, the control circuit operates in a second mode with a first state to close the first and third switches, and a second state to close the fourth switch to connect the inductor in series with the flying capacitor. Dual mode operation of the first and second stages facilitates buck-boost operation with reduced inductor losses and converter switching losses, and the integrated circuit can be used in boost, buck or other configurations.

Abstract: The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

Abstract: A system includes an LLC converter to convert an input DC voltage to an output DC voltage. A burst generator generates a switching signal having a burst time and a sleep time to operate the LLC converter when output load current of the LLC converter is below a predetermined threshold. A burst power calculator adjusts the sleep time for the switching signal such that output power of the LLC converter during the burst time is held substantially constant with respect to changes in the output load current.

Abstract: Disclosed examples include a programmable attenuator circuit providing selective cross coupling of impedance components between circuit input nodes and output nodes according to control signals to set or adjust an attenuation value of the attenuator circuit. The attenuator circuit includes a plurality of attenuator impedance components, and a switching circuit to selectively connect at least a first attenuator impedance component between the first input node and the second output node, to selectively connect at least a second attenuator impedance component between the second input node and the first output node, to selectively connect a third attenuator impedance component between the first input node and the first output node, and to selectively connect a fourth attenuator impedance component between the second input node and the second output node.

Abstract: A method of transmitting association requests in a wireless sensor network includes transmitting an association request from a leaf node to an intermediate node. The method further includes transmitting the association request from the intermediate node during one of either a shared time slot or a dedicated time slot in response to at least one of the timing of dedicated time slots and data collision rates during shared time slots.

Abstract: A voltage regulator includes a measurement circuit for obtaining a value representing a magnitude of an output capacitance connected at an output node of the voltage regulator. A correction circuit in the voltage regulator modifies a compensation circuit internal to the voltage regulator based on the value. The modification of the compensation circuit is done to ensure that sufficient stability margins to accommodate the output capacitance are ensured for the main feedback loop in the voltage regulator. In an embodiment, a voltage proportional to the output capacitance is detected at start-up of the voltage regulator, and a corresponding binary signal is generated. The logic value of the binary signal is used to add or remove components and/or circuit portions in the compensation circuit to ensure stability. The voltage regulator is thus designed to support a wide range of output capacitance values.

Abstract: A system and method is disclosed for monitoring current consumption of various subsystems and applications and adjusting functional parameters to ensure a constant current drain from the battery. The constant current drain can be dynamically adjusted based on a predetermined amount of battery life. A user can determine the amount of battery life to be required and the system adjusts current consumption of various subsystem components and applications to provide consistent and predictable battery life.

Abstract: The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

Abstract: An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.

Abstract: Methods and apparatus for reduced bandwidth pulse width modulation are disclosed. A system includes a digital controller circuit coupled to a data interface, the digital controller circuit configured to receive image data for display and further configured to encode line data for transmission to a spatial light modulator using a data compression scheme; and the spatial light modulator coupled to the data interface and configured to receive encoded data and to decode the encoded data to produce unencoded data corresponding to pixel data for display on an array of pixel elements in the spatial light modulator; wherein data transmitted from the digital controller circuit to the spatial light modulator further comprises encoded data that is formed from bit planes using a data compression scheme to form partial lines of data. Additional methods and apparatus are disclosed.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A method and apparatus for encoding and decoding video data. Including context encoding or decoding at least two bins of each significant transform coefficient in an array of transform coefficients and bypass encoding or decoding a sign indicator for each significant transform coefficient in an array related to a block of an image.

Abstract: System and methods for using channel quality reports to reduce inter-band interference are disclosed. Channel information is received at a first wireless communication device from a second wireless communication device. The first wireless device is operating in a first frequency range, and the second wireless device is operating in a second frequency range. The first frequency range is adjacent to the second frequency range. A channel quality report is generated at the first wireless communication device. The channel quality report indicates that particular sub-bands in the first frequency range have low channel quality. The particular sub-bands are selected using the channel information.

Abstract: A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a near field communication (NFC) coupler located on the substrate. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a field confiner located between the NFC coupler and the port region on the housing configured to guide electromagnetic energy emanated from the NFC coupler through the port region to a port region of an adjacent module.

Abstract: A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.

Abstract: At least first nodes and second nodes of a decision tree are stored within a memory of an information handling system. The first nodes include a first parent node and first remaining nodes that descend from the first parent node. The second nodes include a second parent node and second remaining nodes that descend from the second parent node. The first nodes are grouped into a first packed node stored in first physically contiguous locations of the memory. The first nodes are sequenced in the first physically contiguous locations according to respective depth levels of the first nodes within the decision tree. The second nodes are grouped into a second packed node stored in second physically contiguous locations of the memory. The second nodes are sequenced in the second physically contiguous locations according to respective depth levels of the second nodes within the decision tree.

Abstract: Suppression of interference across transceivers integrated on a single semiconductor chip. An example of a method of reducing noise in a transceiver includes introducing an adjustable time delay into a signal between a first section of a signal path into which noise may be introduced and a second section of the signal path into which noise may be introduced. The method also includes selectively adjusting the time delay and signal polarity to improve a signal-to-noise metric of the transceiver. An example of the transceiver includes a transmitter and a receiver. The transceiver also includes an adjustable time delay between a first section of a transceiver signal path into which noise may be introduced and a second section of the transceiver signal path into which noise may be introduced and circuitry for reducing noise by adjusting a value of the time delay.