Abstract: A circuit includes a generating circuit that generates a current signal in response to an input signal, a first one of a plurality of integrators that generates a voltage signal from the current signal, a comparator that is responsive to the voltage signal to compare the voltage signal with a predefined voltage, a switching circuit that reconfigures a first capacitor and a second capacitor connected to the first one of the plurality of integrators to discharge the first capacitor and to enable the second capacitor to generate the voltage signal in response to the current signal, and an analog-to-digital converter to generate an output when a predefined time interval has elapsed. The output is obtained by adding a first charge value corresponding to a count of number of times the voltage signal reaches the predefined voltage in the predefined time interval and a second charge value from the analog-to-digital converter.

Abstract: A voltage control mode buck converter circuit includes a feedback amplifier providing a comparison signal and a storage circuit in communication with the comparison signal to store a storage comparison signal value. The storage circuit stores the operating conditions for the circuit during normal continuous conduction mode operation in response to sensing a load drop for the circuit. A switching circuit locks the feedback amplifier into the stored operating parameters while the converter circuit operates in non-continuous conduction mode. When the circuit transitions back into the continuous conduction operation mode, the feedback amplifier is already operating at conditions that are compatible with a continuous conduction operation mode.

Abstract: One aspect of an LED package, which is covered by this disclosure, includes at least two LED emitters located on a substrate wherein each of the at least two LED emitters forms an emitting area. The emitting area is substantially equal to a reflective area of the LED package, and the LED package has an optical axis that is substantially non-parallel to an optical axis of each of the at least two LED emitters.

Abstract: A sequence of image frames are processed to determine if a pair of image frames in the sequence contain a same content, but have different global luminances. If the global luminances are different despite the content being the same, the global luminance of one of the image frames in the pair is adjusted to reduce the difference in the global luminances. The global luminance-adjusted image frames may be provided for further processing operations such as compression and global image stabilization. Reducing the global luminance difference may provide benefits such as improvements to compression and global image stabilization.

Abstract: A vertical drain extended metal-oxide semiconductor field effect (MOSFET) transistor or a vertical double diffused metal-oxide semiconductor (VDMOS) transistor includes: a buried layer having a first conductivity type in a semiconductor backgate having a second conductivity type; an epitaxial (EPI) layer having the first conductivity type and formed above the buried layer; a deep well having the first conductivity type in the EPI layer extending down to the buried layer; at least one shallow well having the second conductivity type in the EPI layer; a shallow implant region having the first conductivity type and formed in the shallow well; a gate electrode having a lateral component extending over an edge of the shallow well and stopping at some spacing from an edge of the shallow implant and having a vertical trench field plate extending vertically into the EPI layer.

Abstract: This invention modifies an irregular software pipelined loop conditioned upon data in a condition register in a compiler scheduled very long instruction word data processor to prevent over-execution upon loop exit. The method replaces a register modifying instruction with an instruction conditional upon the inverse condition register if possible. The method inserts a conditional register move instruction to a previously unused register within the loop if possible without disturbing the schedule. Then a restoring instruction is added after the loop. Alternatively, both these two functions can be performed by a delayed register move instruction. Instruction insertion is into a previously unused instruction slot of an execute packet. These changes can be performed manually or automatically by the compiler.

Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

Abstract: In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. Each of the caches comprises a plurality of cache lines, and each cache line is associated with a way. The software also causes the processor to reassign the way of a cache line to a different way.

Abstract: The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate.

Abstract: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.

Abstract: In one aspect, a method for protection of an integrated circuit device includes but is not limited to detecting a first current in the integrated circuit device, wherein the first current is caused by a second current; and shunting the second current away from the integrated circuit device in response to detecting the first current. Such detecting may include but not be limited to detecting the first current by detecting a voltage drop across a sensing resistor, which may include but not be limited to using at least two sensing transistors. Such shunting may include but not be limited to using at least one shunting transistor.

Abstract: An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of polysilicon and depositing a second layer of polysilicon over the layer of dielectric. The method further includes implanting an equivalent concentration of implant in both the first layer of polysilicon into the second layer of polysilicon.

Abstract: One embodiment of the invention includes a current mirror system. The system comprises a master circuit configured to conduct a first current in response to an activation state of an activation signal. The system also comprises a slave circuit configured to generate at least one second additional current in response to the activation state of the activation signal. Each of the at least one additional current can be proportional to the first current. The system further comprises a current path circuit that is configured as a substantial copy of the master circuit, the current path circuit being configured to conduct the first current in response to a deactivation state of the activation signal.

Abstract: An enhanced direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response information, which contains the channel and valid byte count. The EDMA stores the read data into a write buffer and acknowledges to the source port that the EDMA can accept more data. The read response and data can come from more than one port and belong to different channels. Removing channel prioritizing according to this invention allows the EDMA to store read data in the write buffer and the EDMA then can acknowledge the port read response concurrently across all channels. This improves the EDMA inbound and outbound data flow dramatically.

Abstract: A method is provided of fabricating a thin film resistor semiconductor structure. In one aspect of the invention, the method includes forming a dielectric layer over a semiconductor substrate, forming a thin film resistor on the dielectric layer, and annealing the thin film resistor at a substantially high temperature for a predetermined time period to set the thermal coefficient of resistance of the thin film resistor. A passivation layer is formed over the semiconductor structure.

Abstract: A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster level switch network. Transfer instructions issue in dedicated instruction issue slots in parallel with instructions that perform computation in functional units. The switch network can perform permutations on the data being moved. The switch network enables for operands to be broadcast between the sub-clusters, global register file and memory.

Abstract: The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.