Abstract: Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor.

Abstract: Example embodiments of the systems and methods of variable fractional rate digital resampling as disclosed herein achieve variable rate conversion. In the example embodiments, the input samples are upsampled by a factor N in an upsampler followed by a filter which then goes through a linear interpolator. The filter cleans the spectral images of the signal created due to the upsampling operation.

Abstract: A DC-DC converter, having an input voltage and an output voltage, includes an inductor and a switch switching the input voltage to an input side of the inductor, where a feedback path controlling initiation of closing the switch includes capacitive coupling of the voltage at the input side of the inductor.

Abstract: A driver circuit includes an input drive stage, an output drive stage, and a transformer. The input drive stage is configured to receive a differential input signal, and amplify the differential input signal. The output drive stage is coupled to the input drive stage, and is configured to receive amplified differential input signal from the input drive stage, and to further amplify the amplified differential input signal. The transformer is configured to transfer current from the output drive stage to the input drive stage.

Abstract: A method of forming a packaged electronic device includes fabricating a MEMS structure, such as a BAW structure, on a first semiconductor wafer substrate; forming a cavity in a second semiconductor wafer substrate; and mounting the second substrate on the first substrate such that the MEMS structure is positioned inside the cavity in the second substrate. A wafer level assembly and an integrated circuit package are also described.

Abstract: Methods of reducing power consumption in a USB power-delivery source device. In one such method, one or more source capabilities messages are sent by the USB power-delivery source device. If, after sending a source capabilities message, a response to said source capabilities message is not received within a predetermined time period, the device sends another source capabilities message. If, after sending a predetermined number of source capabilities messages, no response is received, the device waits an extended period of time before sending another source capabilities message. Receiving functionality of the USB power-delivery source device is turned off during some or all of said extended period of time.

Abstract: According to exemplary embodiments, a system and method for automated system power supply design is provided. The system and method enables circuit designers to quickly and independently design complicated single or multi rail power supply systems including multiple loads and sequencing requirements. The power solutions offered to designers may include all required power supplies to power up the loads including sequencers and load switches. The power supply design system may be implemented on a standalone processing unit, a distributed computing network, internet based web application, or among various other network applications.

Abstract: Cascaded buck boost DC to DC conversion systems, controllers and methods are presented, in which a buck converter stage is pulse width modulated in a first mode and a boost converter stage is pulse width modulated in a second mode, with the pulse width modulation using a first one of peak current control in valley current control in the first mode, and using the other of peak current control in valley current control in the second mode, and operation is switched between the first and second modes based on an on-time of a low side driver switch of the buck converter stage or the boost converter stage.

Abstract: A capacitive touch keypad may receive a touch by a conductive object to one or more keys of the keypad, in which the keys each have a separate capacitive key electrode. The touched locations may be determined by precharging a pseudo-randomly selected set of key electrodes a number (M) of iterations while the keyboard is being touched, producing a sense voltage for each iteration by coupling all of the key electrodes to a reference capacitor, producing a 1-bit sense measurement for each iteration by comparing the sense voltage to a reference voltage to form a set of M 1-bit sense measurement, and by applying a modified binary iterative hard threshold (BIHT) algorithm to the set of M 1-bit sense measurements, in which only the non-zero locations of the solution are monitored in each iteration.

Abstract: A broadcast/multicast transmission format includes a data portion and a cyclic prefix (CP) coupled to the traffic data portion. A method and system for providing broadcast/multicast transmissions with the application to communication systems that perform broadcast or multicast transmission is also disclosed. The addition of a pilot to the data portion of the transmissions is also disclosed.

Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

Abstract: An apparatus and method are provided to determine the occurrence and location of an interaction with an interface, particularly with an image of a user interface that may be projected or otherwise produced on a surface. The apparatus uses one or more single-element sensors (such as a photodiode) to sense and capture light readings of a scene, the readings corresponding to a plurality of structured light images injected within the presentation of the interface. The readings are compared to a baseline set of readings to determine the occurrence and location of an interaction event by an obstacle (i.e., a finger or a stylus) such as a touch event or a movement of the obstacle.

Abstract: A method of analyzing a digital camera includes generating first image data using an image sensor in the camera. A first analysis is performed on at least one portion of the first image data. Second image data is generated using the image sensor and a second analysis is performed on the at least one portion of the second image data. The results of the first analysis are compared to the results of the second analysis. A signal indicating a fault with the digital camera is generated in response to the first analysis differing from the second analysis by a predetermined amount.

Abstract: A vertically oriented BARITT diode is formed in an integrated circuit. The BARITT diode has a source proximate to the top surface of the substrate of the integrated circuit, a drift region immediately below the source in the semiconductor material of the substrate, and a collector in the semiconductor material of the substrate immediately below the drift region. A dielectric isolation structure laterally surrounds the drift region, extending from the source to the collector. The source may optionally include a silicon germanium layer or may optionally include a schottky barrier contact.

Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.

Abstract: Method of forming a termination angle in a titanium tungsten layer include providing a titanium tungsten layer and applying a photo resist material to the titanium tungsten layer. The photo resist material is exposed under a defocus condition to generate a resist mask, wherein an edge of the exposed photo resist material corresponds to the sloped termination. The titanium tungsten layer is etched with an etching material, wherein the etching material at least partially etches the photo resist material exposed under the defocused condition, and wherein the etching results in the sloped termination in the titanium tungsten layer.

Abstract: Embodiments of the invention relate to automatic test equipment for testing a circuit having an oscillating crystal and to a method for operating such automatic test equipment. A generator generates a first signal comprising an oscillating part having at least one predetermined frequency. A first terminal couples the first signal to the oscillating crystal. At least one predetermined frequency is located inside a predetermined window around one of the resonance frequencies of the oscillating crystal. An analyzer has a second terminal coupled to the oscillating crystal for detecting a second signal and a rectifier connected in series with a low-pass filter for rectifying and filtering the second signal. A detector for detects a DC-signal at the output of the low-pass filter and for signals a valid test result for the oscillating crystal if the DC-signal exceeds a certain threshold value.

Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.