Abstract: In a method and system for evaluating sub-critical fatigue crack growth in a semiconductor device, a plurality of energy pulses generated by an energy source are repeatedly impinged onto the semiconductor device for a predefined time interval. The repeated impinging of the plurality of energy pulses induces a mechanical stress within the semiconductor device. The induced mechanical stress, maintained below a threshold and repeated for a predefined number of cycles, causes a formation of a sub-critical fatigue crack within the semiconductor device. A detector detects the presence of the sub-critical fatigue crack leading to a fatigue failure. A rapid determination of a pass or fail status for a fatigue test of the semiconductor device is made by comparing a total number of cycles to fatigue failure to a predefined benchmark.

Abstract: A mesh point operable in a decentralized wireless network is provided. The mesh point includes a transceiver and a processor. The transceiver is operable to communicate with other mesh points. The processor is programmed to execute a routing protocol such that, when a first policy of the routing protocol is selected and a transmission failure occurs between the mesh point and a current parent node of the mesh point, the processor is operable to execute instructions to promote finding another route to a root. The other route to the root is found by referencing a topology, if the topology is available, to identify the route to the root. If the route is not found, the transceiver transmits a one-hop broadcast route request. If the route is still not found, the mesh point enters a route discovery state.

Abstract: A method of correctly estimating the frequency offset when the CPE modem has already acquired and is tracking the OFDM burst boundaries in an OFDM-based, wireless communication system. CPS data in an OFDM-based, wireless communication system is modulated as QPSK data in the training tones of the data burst. As long as some bursts have the CPS data modulation and some bursts do not have the CPS data modulation, the CPS data can be recovered. A slip results when there is a linear phase difference across the tones (after the FFT) between the current and the previous burst. This linear phase difference is generally taken care of by the channel estimation obtained using the pilot tones. This phase difference is however, now compensated for correct frequency offset estimation which occurs before the channel estimation and CPS decoding steps.

Abstract: A circuit provides a reduced harmonic content output signal OUTA and/or OUTB that is modulated according to an input signal 231. The circuit has an oscillator circuit 210 and a harmonic rejection mixer (HRM) 230. The oscillator circuit 210 includes at least one “circuit portion” (FIG. 2A) configured to receive first and second orthogonal oscillator input signals (two of I, I?, Q, Q?) having respective first and second phases, and to provide an arbitrarily large number of oscillator output signals (?M) having respective mutually distinct phases that are interpolated between the first and second phases. Harmonic rejection mixer 230 is configured to use the input signal to modulate a combination of the oscillator output signals, the oscillator output signals being respectively weighted so as to provide an emulated sinusoidal signal constituting the reduced harmonic content output signal.

Abstract: A method for removing material from the surface of a semiconductor wafer with a chemical mechanical polishing process is described. The method uses a polishing pad on which a line-pattern of grooves is formed. The pattern comprises orderly spaced grooved-area and area without grooves. The method combines information of the surface topography of the wafer, the nature of the material to be removed, and the available groove pattern on the surface of the polishing pad to generate a process recipe in which the resident time of portions of the semiconductor wafer spends at the grooved and un-grooved areas of the polishing pad during the chemical mechanical polishing process is pre-determined.

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.

Abstract: An oscillating torsional hinged device, such as a mirror, having the advantages of an oscillating device with permanent magnets mounted on the hinges, but without excessive size is disclosed. The permanent magnets are mounted in the areas of the anchor members rather than directly on the hinges.

Abstract: A current-domain transmitter is configured to receive an input signal and provide a transmitted signal. The transmitter has a plurality of elements, operatively arranged between the input signal and the transmitted signal and configured to represent the input signal with respective electric currents whose respective current magnitudes are each substantially proportional to the input signal. The elements may include a current-steering digital-to-analog converter (DAC), a current mode filter (such as an LPF), a current mode mixer, and/or a current mode amplifier.

Abstract: A method and motor controller for sensing motor winding current. An FET drive transistor has its ON resistance periodically increased to about five times the normal ON resistance for short sensing intervals during motor drive. An analog-to-digital converting senses the voltage across this FET during the sensing intervals. The resulting digital signal is used to calculate motor current. The time at high ON resistance is much less than the time at normal. The ON resistance can be changed using two FETs or one FET with gate fingers over differing parts of the channel region.

Abstract: Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.

Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

Abstract: High side extended-drain MOS driver transistors (T2) are presented in which an extended drain (108, 156) is separated from a first buried layer (120) by a second buried layer (130), wherein an internal or external diode (148) is coupled between the first buried layer (120) and the extended drain (108, 156) to increase the breakdown voltage.

Abstract: An efficient framing scheme is described for the transmission of frame overhead data in next generation ADSL modems. As a result of this new framing scheme, the available data rate for the transmission of payload data increases. High payload data rates and consequently wider reach of the ADSL modem are the most important performance requirements and customer care-abouts for ADSL modems. This application explains the new framing scheme in detail and provides examples for the computation of the framing parameters.

Abstract: A digital micromirror device (DMD) modified for use as a temporal light modulator. The DMD is modified so that the mirrors of the DMD have a preferential tilt direction. The inputs and outputs of the DMD are connected to common ground, except for the bias input lines. The latter are connected to a common excitation input, which is used to cyclically reposition the mirrors between tilted and flat states.

Abstract: Systems, methods and circuits for generating random numbers. As one example, a system for generating random numbers is disclosed that includes an analog to digital conversion element that provides an output, and a digital filter that is electrically coupled to the analog to digital conversion element and provides an information signal based at least in part on the output. In addition, the system includes a memory device electrically coupled to a sequencer that generates a capture signal. The memory is operable to capture the information signal based at least in part on the capture signal.

Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

Abstract: A processor that includes a memory comprising a condition code register (CCR) and a plurality of execution units coupled to the memory. Each execution unit comprises multiple stages and is provided with a different instruction predicated on a conditional statement. The conditional statement of each different instruction also is provided to a single execution unit. The single execution unit compares the conditional statement of each different instruction to the CCR in a single stage of the single execution unit.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).

Abstract: A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.

Abstract: A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.