Abstract: An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.

Abstract: A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface layer; a base contact (130 and 131) extending through a substantial portion (141) of the surface layer, spaced apart (140a) from the emitter; an insulator region (150/151) buried under the base contact; a collector contact (120); and a first polycrystalline semiconductor region (152/153) selectively located under the insulator region, and a second polycrystalline semiconductor region (154) selectively located under the collector contact. These polycrystalline regions exhibit heavy dopant concentrations of the first conductivity type; consequently, they lower the collector resistance.

Abstract: A low cost antenna in a base station suitable for deployment where high density of wireless users are present in specific directions (e.g., cross roads in urban areas). A lens is used associated with antenna elements to collimate the beam for a longer distance in the desired directions. By using the lens, the need for complex electronics is minimized, thereby reducing the cost of a base station. Another aspect of the present invention enables the lens to be designed precisely by first determining the radiation pattern of each array element according to a corresponding coordinate system, transforming the radiation pattern to a common coordinate system, and determining a composite radiation pattern using the value determined for the common coordinate system. Inverse scattering technique is applied using the composite radiation pattern and the desired collimation pattern to determine the precise shape of the lens.

Abstract: Integrated circuit die on wafer are tested individually, without probing any of the die, using circuitry (TC1–8, BC1–8, LR1–8, RR1–8, PA1–PA4) provided on the wafer.

Abstract: A method of decoding in layers data received in a communication system, comprising receiving a codeword containing a plurality of elements and translating the plurality of elements into probability values by dividing the rows of at least one column of a parity check matrix associated with the codeword into groups and processing at least some of the groups separately.

Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

Abstract: The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

Abstract: A static random-access memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) a row of SRAM cells coupled to a word line and a power source configured to vary in voltage to enable the row of SRAM cells to operate in a retain-till-accessed (RTA) mode and (2) a word line driver coupled to the power source and configured to drive the word line.

Abstract: The present invention provides a semiconductor device, a method for manufacturing therefore, and an integrated circuit including the same. The semiconductor device, in one advantageous embodiment, includes a gate structure (230) located over a substrate (210), and a source/drain region (250) located within the substrate (210) and proximate the gate structure (230).

Abstract: Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and power supplies such that it does not load functional circuit signals nor consume power.

Abstract: The present invention provides a method for manufacturing a digital micromirror device and a method for manufacturing a projection display system. The method for manufacturing the digital micromirror device, without limitation, may include providing a material stack (130), the material stack (130) including a spacer layer (140) having one or more openings (145) therein and located over control circuitry (110) located on or in a semiconductor substrate (105), a layer of hinge material (150) located over the spacer layer (140) and within the one or more openings (145), and a layer of hinge support material (160) located over the layer of hinge material (150) and within the one or more openings (145).

Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.

Abstract: The present invention provides a method for removing photoresist, and a method for manufacturing a semiconductor device. The method for removing photoresist, without limitation, may include subjecting a photoresist layer (210) located over a substrate (110) to a thermal bake (410) in the presence of hydrogen, and then removing the photoresist layer (210).

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and an integrated circuit including the same. The semiconductor device (300), without limitation, may include a gate electrode (320) having a gate length (l) and a gate width (w) located over a substrate (310) and a gate electrode material feature (330) located adjacent a gate width (w) side of the gate electrode (320). The semiconductor device (300) may further include a silicide region (350) located over the substrate (310) proximate a side of the gate electrode (320), the gate electrode material feature (330) breaking the silicided region (350) into multiple silicide portions (353, 355, 358).

Abstract: The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes at least one write transistor. The circuitry also includes a read circuit coupled to the SRAM cell core that includes at least one read transistor having a gate signal in common with the gate signal of the write transistor. The read transistor and the write transistor share a common gate signal, and each have an electrical characteristic, for which the electrical characteristic of the read transistor differs from that of the write transistor.

Abstract: Context-based adapative binary arithmetic coding (CABAC), as used in video standards such as H.264/AVC, with a renormalization of the interval low value plus range that includes partitioning of the bits of the low value to provide output bits plus low value update without bit-level iterations or aggregation of output bits until a full byte can be output.

Abstract: Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).

Abstract: A wireless communications system is presented where a mobile station is able to automatically determine its proximity to a second mobile station or landline telephone. Once the proximity determination command has been given, no further actions are required by the users of either telephone. A GPS receiver connected to the first mobile station is able to provide that mobile with its position and direction. The first mobile station makes a request to the other telephone for its position, through SMS messaging for example. A GPS receiver connected to the second mobile station is able to provide the second mobile station with data to enable the position request. Trust determinations can be enabled so that position data is sent to a restricted list of requesting telephone numbers. Likewise, the second mobile station can request position data from the first mobile station. When position information is requested from a landline telephone, the request can be fulfilled by the landline telephone service provider.

Abstract: A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclose& The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates.

Abstract: A system and method to measure the clock skew between transmitting and receiving devices operating with independent clock sources over a packet network is described. To provide adaptive playout in an IP telephony device without a sequencing scheme in the packets, the clock skew is measured and recorded. Using a PCM resampler that is implemented with an interpolation filter bank of FIR subfilters, the change in depth of the playout buffer during transmission is analyzed, and this change infers the clock rate associated with the transmission.