Patents Assigned to Texas Instruments
  • Reducing time to design integrated circuits including performing electro-migration check
    Patent number: 7197730
    Abstract: The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or more) of the early stages may ensure that the load limit is not violated. Techniques such as increasing the path width and inserting additional circuit (e.g., a buffer cell) in the path, may be employed to avoid the EM violations. As a result, unneeded iterations of design stages may be avoided for purposes of EM checks alone.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Ananth Somayaji Goda, Kalpesh Amrutlal Shah, Prapanna Tiwari, Sugandhini Karunanidhi, Venugopal Puvvada
  • Integrated circuit dynamic parameter management in response to dynamic energy evaluation
    Patent number: 7197733
    Abstract: A single integrated circuit (12). The integrated circuit comprises a first circuit (14x) having a data path, the first circuit consisting of a first number of logic gates for performing a plurality of logic functions. The integrated circuit also comprises a circuit (22x) for indicating a potential speed capability of the data path. The circuit for indicating comprises a second number of logic gates (82, 92) for performing the plurality of logic functions, wherein the second number is less than the first number. The circuit for indicating also comprises additional circuitry (88, 98) for representing parasitic characteristics in the data path.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Sami Issa, Baher Haroun, Shakti S Rath
  • Amplifier switching control circuit and method for current shunt instrumentation amplifier having extended position and negative input common mode range
    Patent number: 7196581
    Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a generally parallel configuration, each with inputs coupled through the same pair of matched input resistors which receive a differential input signal that may have both a positive and negative common mode range. An offset adjustment amplifier (17) receives a differential error signal representative of the difference between offset voltages of the first and second operational amplifiers and generates offset adjustment signals that are applied to input stages of the first and second operational amplifiers to adjust their respective offset voltages so as to equalize them.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Gammie, Sergey V. Alenin
  • Ultra-thin sample preparation for transmission electron microscopy
    Patent number: 7196338
    Abstract: In accordance with the invention, there is a method of fabricating a material for transmission electron microscopy comprising removing a first portion from a material having a thickness of (d1) to form a thinned material having a thickness of (d2), contacting the thinned material to a sacrificial layer having a thickness of (s1), and removing a second portion from the thinned material so the thinned material has a thickness of (d3), wherein (d3)<(d2).
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Nathan V. Holloway
  • Fast-response current limiting
    Patent number: 7196585
    Abstract: An amplifier (10?) has a first amplifier stage (14) for producing a control current (IX) in response to an input voltage. A second amplifier stage (16) has first (46) and second (38) transistors. The first transistor (46) is coupled to receive the control current (IX) and is operable to produce a control voltage. The second transistor (38) is coupled to receive the control voltage and operable to produce an output current. A nonlinear resistive element (50) is coupled to the first transistor (46) to add a nonlinear function of the control current (IX) to the control voltage. The nonlinear resistive element (50) may include a third transistor connected between the first transistor (46) and a reference potential, operable to receive the control current (IX) and to generate the nonlinear function thereof.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Roy Alan Hastings, Lemuel Herbert Thompson, II
  • Relaxation oscillator based keypad decoder
    Patent number: 7196640
    Abstract: The keypad interface element of this invention uses a relaxation oscillator and a digital keypad processor having a counter/timer to decode specific keys. The RC portion of the relaxation oscillator includes a resistance ladder and a set of momentary on pushbutton switches disposed change resistance dependent upon which key is pressed. This causes the relaxation oscillator to produce an output signal having a corresponding frequency. The counter/timer of the digital keypad processor produces a count corresponding to the oscillator frequency. The digital keypad processor latches and holds a binary number specifically identifying the depressed key. A state machine in the digital keypad processor provides transient-free, noise immune keypad decoding.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen J. Fedigan
  • Direct RF sampling for cable applications and other broadband signals
    Patent number: 7197524
    Abstract: A sampling method implements direct RF sampling of the down-stream DOCSIS and Euro-DOCSIS cable plant signals present at the customer premises equipment (CPE).
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Nir Sasson, Uri Garbi, Naor Goldman
  • Versatile system for wafer edge remediation
    Patent number: 7195679
    Abstract: The present invention provides a system (200, 300) for remediating aberrations along the perimeter of a semiconductor wafer (202). The system includes a cleaning apparatus (204) within which the wafer is spun within a confined area. A chuck (208) defines the confined area, having a sidewall that extends above the upper surface (214) of the wafer and surrounds the perimeter of the wafer. The chuck also has a bottom wall, with an aperture formed therein, beneath the wafer. The system includes an isolation barrier (220), disposed atop the bottom wall of the chuck and around the aperture, in proximity to the lower surface so of the wafer. This forms a narrow gap (226) between the barrier and the wafer. A pressurized source forcefully directs a gas (218) at and along the lower surface of the wafer. The system also includes a remediation solution (228) that is applied to the upper surface of the wafer.
    Type: Grant
    Filed: June 21, 2003
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Changfeng Xia, Trace Q. Hurd
  • Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies
    Patent number: 7195984
    Abstract: An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Joe R. Trogolo, William Loftin, William F. Kyser, Jr.
  • High frequency balanced phase interpolator
    Patent number: 7196564
    Abstract: A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an output and a second portion of the first modulated input signal to an internal balancing node. The weighting system also is configured to steer a first portion of the second modulated input signal to the output and a second portion of the second modulated input signal to the balancing node. The first portion of the first and second modulated input signals are summed at the output to provide an interpolated output signal having a phase angle that is between the first and second phase angles.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Narasimhan Trichy Rajagopal, Bradley A. Kramer
  • Resolver arrangement
    Patent number: 7196643
    Abstract: A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing channels each of which has an analog input connected a different one of the stator coils and a channel output. Each of the processing channels includes a sigma-delta modulator with an output that supplies a bit-stream representative of an analog input signal received from a respective stator coil. Each channel also includes a first digital filter that receives the bit-stream from the sigma-delta modulator and converts the bit-stream to intermediate digital data-words. In addition, each channel has a digital synchronous demodulator that demodulates the intermediate digital data-words in synchronism with the carrier signal providing demodulated data-words.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Frank Ohnhaeuser, Michael Reinhold, Mikael Badenius
  • CMTS architecture based on ethernet interface locatable in a fiber node
    Patent number: 7197045
    Abstract: A communication device (116, 216, 316, 416) for a communications network having a first integrated circuit (IC) (141, 244, 344, 444) including one or more receivers (136, 236, 336) and a first MAC function (140, 240, 340), and a second IC (139, 242, 342, 442) including one or more transmitters (134, 234, 334) and a second MAC function (138, 238, 338). The first (141, 244, 344, 444) and second (139, 242, 342, 442) IC's are coupleable to a communications network for controlling the downstream and upstream communications, respectively.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Mati Amit
  • Multiple processor cellular radio
    Patent number: 7197623
    Abstract: Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The Protocol Processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Francis Aussedat, Pierre Calippe
  • Formation of gate dielectrics with uniform nitrogen distribution
    Publication number: 20070066021
    Abstract: The present invention provides a method for manufacturing a gate dielectric (710) that includes providing a nitrided dielectric layer (220) over a substrate (120). The nitrided dielectric layer (220) has a nonuniform concentration of nitrogen in a bulk thereof. The nitrided dielectric layer (220) is exposed to oxygen radicals (410), resulting in a reduction of the non-uniformity.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 22, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Hiroaki Niimi, Reima Laaksonen
  • Method for chemical mechanical planarization of a metal layer located over a photoresist layer and a method for manufacturing a micro pixel array using the same
    Publication number: 20070066063
    Abstract: The present invention provides a method for planarizing a metal layer, and a method for manufacturing a micro pixel array. The method for planarizing the metal layer, without limitation, may include the steps of forming a metal layer over a photoresist layer, and then planarizing the metal layer using a chemical mechanical planarization process.
    Type: Application
    Filed: September 20, 2005
    Publication date: March 22, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Anthony DiCarlo, Jingqiu Chen, Yanghua He, James Baker, David Rothenbury
  • Method and system for preventing unsecure memory accesses
    Publication number: 20070067826
    Abstract: A system comprising a processor adapted to activate multiple privilege levels for the system, a monitoring unit coupled to the processor and employing security rules pertaining to the multiple privilege levels, and a memory management unit (MMU) coupled to the monitoring unit and adapted to partition memory into public and secure memories. If the processor switches privilege levels while the MMU is disabled, the monitoring unit restricts usage of the system. If the processor accesses the public memory while in a privilege level not authorized by the security rules, the monitoring unit restricts usage of the system.
    Type: Application
    Filed: January 30, 2006
    Publication date: March 22, 2007
    Applicant: Texas Instruments Incorporated
    Inventor: Gregory Conti
  • Method to obtain fully silicided gate electrodes
    Publication number: 20070066007
    Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).
    Type: Application
    Filed: September 16, 2005
    Publication date: March 22, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Steven Vitale, Hyesook Hong, Freidoon Mehrad
  • Soft-start circuit and method for power-up of an amplifier circuit
    Publication number: 20070063736
    Abstract: A method and circuit for providing a soft start-up process for an amplifier circuit to reduce or prevent destructive overshoot of an output voltage are provided. In accordance with an exemplary embodiment of the present invention, an exemplary method and circuit are configured to suitably momentarily replace an actual fixed reference voltage with a second reference voltage during the start-up process. Such a method and circuit can provide a fast start-up process without destructive overshoot and without affecting or compromising any control loop of the amplifier circuit, and can be configured within various applications. In accordance with an exemplary embodiment, an exemplary amplifier circuit is configured with a soft-start circuit, with the soft-start circuit configured to provide a secondary reference voltage during initial start-up before switching to an actual reference voltage.
    Type: Application
    Filed: September 19, 2005
    Publication date: March 22, 2007
    Applicant: Texas Instruments Incorporated
    Inventor: Hubert Biagi
  • High performance CMOS transistors using PMD liner stress
    Patent number: 7192894
    Abstract: A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: March 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Haowen Bu, Rajesh Khamankar, Douglas T. Grider
  • System and method for testing gate oxide of an amplifier
    Patent number: 7193469
    Abstract: An amplifier system and method is provided for performing gate oxide integrity (GOI) testing of a power output field effect transistor (FET) of the amplifier system. The amplifier system and method provide for integrated test circuitry that protect drive components during overvoltage stress of a gate of the power output FET, and disables and/or isolates drive devices associated with leakage paths from the gate during gate oxide leakage measurements.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: March 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Cetin Kaya