Abstract: Multiple pixel arrays are enclosed in one single package. The multiple pixel arrays can be disposed in the package with any desired geometric configurations.

Abstract: A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized and counts at each write cycle of the register file and outputs a current count value to the input ports of the register file to pre-load the register file to a known state.

Abstract: Crosstalk can be cancelled in a composite communication signal (ym) which includes a primary signal component associated with communication data and which also includes a crosstalk signal component produced by applying a crosstalk coupling function to crosstalk data. An estimate (R, RCb(0), RCb(?f)AVG) of a statistical characteristic of the crosstalk signal component is obtained from the composite communication signal. A cancellation signal (26, 46) is generated based on the statistical characteristic estimate, and an estimate (29) of the communication data is produced based on the composite communication signal and the cancellation signal.

Abstract: A method is disclosed for allocating processing resources, such as instruction execution which can be measured in MIPs or memory capacity, or other resources of a processor itself or resources used in the process of performing operations, such as memory resources, busses, drivers and the like, to functions in a queue waiting to be executed. This method includes the steps of determining the amount of processor resources available to be assigned, determining an estimate of the amount of resources needed for each function waiting in the queue to execute, and allocating the available resources to the functions using a hierarchical priority scheme. The hierarchical priority scheme assigns priority based on the environmental conditions, the achieved performance, and the amount of resource recently consumed by the function.

Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).

Abstract: A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps around the transistor and thereby increases the width (382) of the transistor (300). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.

Abstract: An apparatus for use with a sensor includes first and second signal treating circuit segments coupled with the sensor for presenting a substantially balanced differential signaling representation of output signals from the sensor. Each respective signal treating circuit segment comprises a plurality of circuit elements having different electrical symmetries coupled in parallel and establishing a plurality of parallel signal paths having asymmetric signal handling characteristics. A feedback circuit is coupled with the first and second signal treating circuit segments and provides feedback signals to selected circuit elements in each of the first and second signal treating circuit segments. The feedback signals effect substantially balanced signal handling among the selected circuit elements having similar electrical symmetries.

Abstract: A compression molding method for forming a mold cap over an integrated circuit structure is provided. A film is positioned adjacent a first die structure such that a mold block coupled to the film is located in a die cavity in the first die structure. The mold block comprises mold compound and at least substantially holding its own shape. An integrated circuit structure including one or more integrated circuit devices coupled to a substrate is positioned adjacent a second die structure. At least one of the first die structure and the second die structure is moved toward the other die structure to cause the integrated circuit structure to compress the mold block within the die cavity in order to form a mold cap covering at least one of the one or more integrated circuit devices.

Abstract: Various preferred processes and equipment are described herein that more efficiently handle residual semiconductor parts during packaging. The processes include picking and removing all of the bad parts from a wafer before picking the good parts and picking all of the good parts first without picking any part necessary to align the wafer. The equipment includes several embodiments of a transfer machine that accommodates the efficient transfer of semiconductor parts between tacky film, waffle packs and tape and reel containment systems. Residual good parts are stored in waffle packs and can be subsequently reused in the packaging process.

Abstract: A system (10) for providing an integer number N of filters. The system comprises an input (Di) for receiving a digital audio signal and an output (Do) for providing a filtered audio signal. The system also comprises circuitry (16) for storing at least a first set of fixed filter coefficients and circuitry for storing estimation data. The system also comprises circuitry (14) for estimating a number of sets of estimated filter coefficients in response to the estimation data and the fixed filter coefficients. The system also comprises circuitry (14) for applying a transfer function to the digital audio signal and in response for providing the filtered audio signal. The circuitry for applying the transfer function applies a set of filter coefficients selected from the first set of fixed filter coefficients and the sets of estimated filter coefficients. Also, the transfer function is selected from a transfer function set consisting of a high pass filter transfer function and a low pass filter transfer function.

Abstract: A write driver (38) produces balanced voltages across head (32) by using the input write data (WDX and WDY) drive transistors of a slower transistor type (typically PNP) on one half of an H-bridge configuration, while transistors of a faster transistor type (typically NPN) in the other half of the H-bridge configuration are driven indirectly by transistors of the slower type, with a trans-resistance in series with transistors of the faster type. Accordingly, the voltage nodes on either side of the write head are pulled to Vcc and Vee symmetrically. A trans-resistance block (40) uses current sources to pull current from capacitive nodes for faster switching.

Abstract: A low noise charge pump circuit includes a first terminal of a first flying capacitor selectively coupled to a first voltage during a first recharging phase and a second terminal of the first flying capacitor selectively coupled to a second voltage during the first recharging phase. The second terminal of the first flying capacitor is coupled to a precharge control circuit during a first parasitic capacitance precharging phase that occurs after the first recharging phase to cause the voltage of the first terminal of the first flying capacitor to equal an output voltage. The first terminal of the first flying capacitor is coupled to an output conductor conducting the output voltage during a first discharging phase that occurs after the first parasitic capacitance precharging phase.

Abstract: A system and method for reordering tones of a DMT signal within a communication system is described. Cross tone correlated noise in a received signal is identified and rearranged such that tones with correlated noise are spread out throughout the received signal before being processed by a decoder such as, Viterbi decoder. In an embodiment, two tones with the most correlated noise are placed at each end of the sequence of tones presented to the Viterbi decoder. In some embodiment, the tones with correlated noise can be spread such that two adjacent tones with correlated noise have a minimum distance of at least three tones between them at the input to the Viterbi decoder. In other embodiment, tones in the received signal can be processed in various kinds of interleavers for reordering according to the interleaver scheme.

Abstract: An operating system (OS) is used in a system with a processor that includes embedded real-time analysis components. The OS includes software objects which provide functionality in response to signals from the embedded real-time analysis components. In an example embodiment, the OS is a real-time OS (RTOS), the embedded real-time analysis components include an embedded event trigger component, and the software objects include a debug object that responds to signals from the embedded event trigger component. For instance, those signals may relate to program flow, data flow, or a hardware operation such as a cache miss, and the debug object may be a breakpoint handler, a trace handler, or an event sequence handler. In the example embodiment, the software objects in the RTOS provide functionality such as stack overflow detection, real-time task priority modification, and/or system scheduling error assertion for a real-time application. Alternative embodiments involve related methods and systems.

Abstract: Computing an absolute difference includes receiving a first value and a second value. Propagate terms are determined according to the first value and the second value at one or more adders (24). The second value is subtracted from the first value using the propagate terms to yield a subtraction difference. It is determined at one or more correctors (26) whether the subtraction difference is negative. If the subtraction difference is negative, the subtraction difference is modified according to the propagate terms to compute an absolute difference between the first value and the second value. Otherwise, the subtraction difference is reported as the absolute difference between the first value and the second value.

Abstract: The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications make the FIFO-DMA interface immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to synchronize the frame transfer on the digital signal processor even if the digital signal processor lacks this functionality. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.

Abstract: A CCD device incorporates Charge Multiplication in its CCD registers together with charge domain Dynamic Range compression. This structure preserves the high dynamic range available in the charge domain of these devices, and avoids limiting it by an inadequate voltage swing of the charge detection nodes and amplifiers. The Dynamic Range compression is logarithmic from a predetermined built in threshold and noiseless. The technique has an additional advantage of maintaining the compact size of the registers, and the registers may also include antiblooming devices to prevent blooming.

Abstract: Processes for the removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the ability to accurately determine the endpoint of the removal step. A vapor phase etchant is used to remove a material that has been deposited on a substrate, with or without other deposited structure thereon. By creating an impedance at the exit of an etching chamber (or downstream thereof), as the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the endpoint of the removal process can be determined. The vapor phase etching process can be flow through, a combination of flow through and pulse, or recirculated back to the etching chamber.

Abstract: The present invention provides, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160, 165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.

Abstract: According to one embodiment, a method for controlling positioning of an optical dithering element includes repeatedly driving the optical dithering element approximately between a plurality of desired positions by a generally periodic drive waveform. During a particular period of the drive waveform, the actual position of the optical dithering element is determined at a plurality of sample times. For each of the determined actual positions of the optical dithering element, a position error indicator is determined based upon whether the magnitude of the actual position is greater than, less than, or the same as a desired setpoint for the position of the optical dithering element. The method also includes generating an error signature for the particular period based on the determined error indicators and modifying the drive waveform in response to the error signature.