Abstract: The present invention facilitates clock and data recovery for serial data streams by selecting a clock phase for each input data transition and generating a recovered clock. In order to identify data transitions, the received serial data stream is sampled N times per ideal bit time, where the minimum value for N must be greater than 2/(1?(2*jitter_ratio)) and jitter_ratio is the fractional representation of the portion of the ideal bit time during which transitions can be expected or estimated to occur. On identifying a transition, a toggle phase is set. In order to avoid stale clock phase selection resulting from jitter and the like, one phase after the toggle phase is blocked or prevented from being selected for the clock. Finally, a clock phase is selected N/2 phases from the toggle phase and a recovered clock is generated by combining the individually selected clock phases.

Abstract: The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance.

Abstract: Wirelessly-linked, distributed resource control (RCS1-RCSn, RCSB, RCC, ARM) supports a wireless communication system (50) for operation in non-exclusive spectrum (24–29). An available resource map (ARM) contains resource availability information gathered by mobile stations (MS1-MSn), and a wired communication channel supports sharing of resource control information among fixed-site stations (BS).

Abstract: Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case throughput rate (without use of SFBs) is computed, and maximization factor equaling a desired throughput rate divided by the worst case throughput rate is computed. A number of SFBs is determined as equaling one less than the maximization factor. By placing the SFBs at appropriate locations in the data transfer path, the desired throughput rate may be attained when transferring large volumes of data.

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: The present invention provides a solution that eliminates both the voltage-controlled oscillator (“VXCO” 105) and its associated D/A converter (120) from the timing recovery scheme, thereby significantly reducing manufacturing costs for modems, such as asymmetric digital subscriber loop (“ADSL”) modems. The present invention also enables tracking of a wider frequency offset. The present invention provides this with a novel timing recovery scheme implemented entirely in the digital domain. The present invention includes a free running clock (205) as the sampling clock for the A/D (110) and D/A (115) converters, and interpolators (210, 220, 615 and 635) to correct timing errors for both the receive and transmit samples. The desired sample can be obtained based on its timing offset and its neighboring samples.

Abstract: A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in rows and columns, (2) bit lines associated with the columns, (3) a high voltage power supply configured to supply a high supply voltage, (4) a low voltage power supply configured to supply a low supply voltage, (5) bit line precharge circuitry configured to precharge at least one of the bit lines to a first voltage and (6) standby circuitry configured to maintain a voltage of the at least one bit line at at least a second voltage, the second voltage being lower than the first voltage and higher than the low supply voltage.

Abstract: The present invention provides a thermostatic biasing controller for use with an integrated circuit. In one embodiment, the thermostatic biasing controller includes a temperature sensing unit configured to determine an operating temperature of the integrated circuit. Additionally, the thermostatic biasing controller also includes a voltage controlling unit coupled to the temperature sensing unit and configured to provide a back-bias voltage corresponding to the operating temperature based on reducing a quiescent current of the integrated circuit.

Abstract: A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.

Abstract: A circuit and method of dithering the switching frequency of an off-line power factor corrected (PFC) pre-regulator. The circuitry used to dither the frequency is advantageously accomplished by taking advantage of the PWM's internal timing circuitry. This invention reduces narrow band EMI and eliminates the need to provide specialty PWM controllers to achieve dithering.

Abstract: A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a very low dielectric constant. Additional benefits are realized by electrically insulating the wires against short-circuiting, by cushioning the wires with a low modulus sheath, and by protecting chip bond pad metallization TABLE 1 Method of Moments Capacitance Models Wire Dimensions 25 × 25 microns Separation between Wires 63.5 microns Distance to ground ?191 microns Model Dielectric Self capacitance Mutual Capacitance constant of Wire 1 Wire 2 separation Model Dielectric Wire 1 Wire 2- Mutual cap constants self cap self cap pf/cm pf/cm pf/cm Plastic encased 4.0 1.03 0.54 1.57 package Cavity package 4./1.0/4. 0.31 0.12 0.43 Foam sheath 4./1./4./1./4. 0.34 0.16 0.50 wires/molded Wires - no 1.? 0.26 0.13 ?0.39.

Abstract: A system for, and method of optimizing an operation of an oversampled filter bank and an oversampled discrete Fourier transform (DFT) filter bank designed by the system or the method. In one embodiment, the system includes: (1) a null space generator configured to produce a basis of a null space of a perfect reconstruction condition matrix based on a first window of the oversampled filter bank and (2) an optimizer associated with the basis generator and configured to employ the null space and an optimization criterion to construct a second window of the oversampled filter bank.

Abstract: A voltage storage cell circuit includes an access transistor and a storage capacitor, wherein the source of said access transistor is connected to a bitline, the gate of said access transistor is connected to a wordline, and wherein the drain of said access transistor is connected to a first plate of said storage capacitor forming a storage node, and wherein the second plate of said storage capacitor is connected to a pump signal. This arrangement allows for a novel pixel circuit design with area requirements comparable to that of a 1T1C DRAM-like pixel cell, but with the advantage of an output voltage swing of the full range allowed by the breakdown voltage of the pass transistor. A spatial light modulator such as a micromirror array can comprise such a voltage storage cell.

Abstract: A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.

Abstract: A fixture (30) adapted to permit the heated exchange of a liner (14) from an operating vertical furnace (10). The fixture is adapted to secure to the base of the liner (14) to both unlock and lower the heated liner, such as a silicon carbide liner, at an controlled rate. The fixture is also adapted to elevate a new liner into the operating vertical furnace at a controlled rate to control the rate of heating of the liner as it is inserted into the operating vertical furnace. The fixture includes an inner ring (34), a low-friction Teflon® ring (36), and an outer ring (38) permitting the rotation of the inner ring within the outer ring. Advantageously, the low friction ring comprises a flanged portion and a vertical portion allowing rotation of the inner ring within the outer ring even when elevated at extreme temperatures exceeding 500° C.

Abstract: The concept of the present invention describes a semiconductor device with a junction 504 between a lightly doped region 501 and a heavily doped region 502, wherein the junction has an elongated portion 504a and curved portions 504b. The doping concentration of the lightly doped region is configured so that it exhibits higher resistivity in the proximity 510 of the curved portion by an amount suitable to lower the electric field strength during device operation and thus to offset the increased field strength caused by the curved portion. As a consequence, the device breakdown voltage in the curved junction portion becomes equal to or greater than the breakdown voltage in the linear portion.

Abstract: In a photo detection arrangement, the current through a detector 10 is sensed by a series resistor Rs and amplified and amplified at 21. The output of the amplifier is compared with a reference voltage 23, which is chosen to correspond to an overload input applied to the detector. When the comparator 22 triggers, a latch 24 is set, which controls a switch 25 to remove the supply voltage to the detector applied to the detector by power amplifier 14. In this way, protection is afforded to the detector 10 without recourse to a high value series resistor. Moreover, the latch provides an output to demonstrate that an overload has occurred.

Abstract: Electrostatic discharge protection circuitry includes a timing circuit operably coupled between the high supply side and low supply side of an associated circuit. The timing circuit has an RC node used for triggering a series of inverters configured to control an ESD dissipation device operably coupled to the high supply side node and the low side supply node of the circuit. A feedback transistor network and a feedback conditioning network is provided for ensuring that the ESD device is held on during an ESD event.

Abstract: A method is provided for automatically optimizing parameter selection in a communication system having one or more channels for transmitting and receiving signals by the steps of: receiving a signal from a channel; characterizing impairments in the channel while gathering statistics using the received signal; analyzing the impairments to obtain recommendations for parameter modifications for improved performance; and modifying the parameters based on the recommendations. Other systems and methods are disclosed.

Abstract: In order to minimize light diffraction along the direction of switching and more particularly light diffraction into the acceptance cone of the collection optics, in the present invention, micromirrors are provided which are not rectangular. Also, in order to minimize the cost of the illumination optics and the size of the display unit of the present invention, the light source is placed orthogonal to the rows (or columns) of the array, and/or the light source is placed orthogonal to a side of the frame defining the active area of the array. The incident light beam, though orthogonal to the sides of the active area, is not however, orthogonal to any substantial portion of sides of the individual micromirrors in the array. Orthogonal sides cause incident light to diffract along the direction of micromirror switching, and result in light ‘leakage’ into the ‘on’ state even if the micromirror is in the ‘off’ state. This light diffraction decreases the contrast ratio of the micromirror.