Abstract: A system for, and method of, noisy automatic speech recognition employing joint compensation of additive and convolutive distortions and a digital signal processor incorporating the system or the method. In one embodiment, the system includes: (1) an additive distortion factor estimator configured to estimate an additive distortion factor, (2) an acoustic model compensator coupled to the additive distortion factor estimator and configured to use estimates of a convolutive distortion factor and the additive distortion factor to compensate acoustic models and recognize a current utterance, (3) an utterance aligner coupled to the acoustic model compensator and configured to align the current utterance using recognition output and (4) a convolutive distortion factor estimator coupled to the utterance aligner and configured to estimate an updated convolutive distortion factor based on the current utterance using first-order differential terms but disregarding log-spectral domain variance terms.

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract: A system for, and method of, noisy automatic speech recognition (ASR) and a digital signal processor (DSP) incorporating the system or the method.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

Abstract: Methods and systems are provided for developing a power management strategy for an application as the application is developed. These methods and systems broadly provide for building the application incorporating a power management module operable to provide several power management methods, capturing power consumption data of the application as it is executed on a target system, accepting modifications to the application to use one or more of the power management methods, and repeating these steps as needed. A power scaling library may also be incorporated in the application and the application may be modified to use the dynamic frequency and voltage scaling functionality provided by the power scaling library.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply tensile strain to channel regions of devices while mitigating masking operations employed. A cap poly layer is formed over NMOS and PMOS regions of a semiconductor device. Then, a resist mask is employed to remove a portion of the cap poly layer from the PMOS region. Subsequently, the same resist mask and/or remaining portion of the cap poly layer is employed to form source/drain regions within the PMOS region by implanting a p-type dopant. Afterward, a cap poly thermal process is performed that causes tensile strain to be induced only in channel regions of devices located within the NMOS region. As a result, channel mobility and/or performance of devices located in the PMOS region is not substantially degraded.

Abstract: A method of operating a wireless communications unit (UE) to request a connection with a base station (10) is disclosed. The wireless unit (UE) receives a signal from the base station (10) indicating at least one time slot within which a preamble may be transmitted by the wireless communications unit (UE). The wireless unit (UE) selects one of a plurality of orthogonal codes (hi) for the preamble and generates a spread code using the selected orthogonal code. The spread code (70) is arranged as a symbol (hi) of the selected code, repeated a selected number of repetitions. The wireless unit (UE) transmits the preamble signal corresponding to the spread code to the base station (10).

Abstract: A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. Temperatures may be computed at various points in the multiprocessor system by monitoring activity information associated with various subsystems. The activity measurements may be used to compute a current power dissipation distribution over the die. If necessary, the tasks in a scenario may be adjusted to reduce power dissipation.

Abstract: A computer implemented method of rasterizing a page in a page description language efficiently utilizes the resources of a multiprocessor integrated circuit by spawning of subtasks from a RISC type processor to one or more DSP type processors. The RISC type processor interprets the page in the page description language and detects a Y coordinate of edge intersection using the floating point calculation unit. The DSP type processors sort polygon edges in increasing Y coordinate and detect a Y coordinate of edge intersections via successive midpoint approximation using an integer multiplier unit.

Abstract: According to one embodiment, a method for providing position feedback for a device includes providing a photointerrupter having a light-emitting diode, a phototransistor, and an aperture between the light-emitting diode and the phototransistor. For a given size aperture, a current through the phototransistor is a function of a current through the light-emitting diode. The method also includes controlling the current through the light-emitting diode current such that a change in the effective aperture size results in a desired approximately proportional change in current through the phototransistor. While controlling the current through the light-emitting diode, a portion of the aperture is blocked by an arm that has a position indicative of the position of the device. The method also includes providing a signal indicative of the change in current through the photodiode as an indication of the change in position of the device.

Abstract: Disclosed are integrated circuits having multiple electromagnetically emissive devices, such as LC oscillators. The devices are formed on an integrated circuit substrate and are given different planar orientations from each other. Particular integrated circuit packages disclosed are “flip-chip” packages, in which solder bumps are provided on the integrated circuit substrate for flipping and mounting of the finished integrated circuit upon a printed circuit board or other substrate. The solder bumps provide conductive connections between the integrated circuit and the substrate. The orientations and positioning of the emissive devices are such that one or more of the solder bumps are interposed between neighboring emissive devices to act as an electromagnetic shield between them.

Abstract: An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.

Abstract: This invention comprises a converged printer architecture for controlling both electro-photographic (EP) processing and raster image processing (RIP) of data for laser modulation over a video line. By converging EP process control with image processing control, significant advantages in cost, image quality, and output stability are achieved. A digital signal processor (DSP) serves as the central processing resource of the architecture. The DSP is well suited for the dual role of image processing and real-time feedback process control. The DSP can operate in open loop motor/motion control, print process control, and in closed loop feedback control including image processing adaptations for quality and stability enhancements.

Abstract: A bottom die and a top die stacked on the bottom die are configured to provide a daisy chain function. Both die include an input/output function control bonding pad (20G), a first bonding pad (20C) controllable to function as either an input or an output, and a second bonding pad (20E) controllable to function as either an output or an electrically floating pad in response to a corresponding input/output function control signal. The top die (30) is stacked on the bottom die (20) and the first bonding pad (20C) of the bottom die (20) is wire bonded to the first bonding pad (30C) of the top die (30). A first reference voltage (VDD) on the function control bonding pad of the bottom die configures its first bonding pad as an output and its second bonding pad as electrically floating, and a second reference voltage (VSS) on the function control bonding pad of the top die configures its first bonding pad as an input and its second bonding pad as an output, to thereby provide the daisy chain function.

Abstract: The present invention discloses a horizontal sync detector circuit (10) comprising a filter portion (12), an equilibrium accumulator portion (14) coupled to the filter portion (12), a horizontal sync detector portion (16) coupled to the filter portion (12) and to the equilibrium accumulator portion (14), and an output logic portion (18) coupled to the horizontal sync detector portion (16), the output logic portion (18) adapted to produce a phase error (116) based on a combination of a coarse phase error (108) and a fine phase error (112).

Abstract: The present invention provides, in one aspect, a microelectronics device 100 that includes a silicon on insulator (SOI) region 110 located over a microelectronics substrate 115. The SOI region 110 comprises a first dielectric layer 120 located over the microelectronics substrate 115, a biasing layer 125 located over the first dielectric layer 120, and a second dielectric layer 130 located over the biasing layer 125. An active region 135 is located over the SOI region 110. Contact plugs 140 extend through the active region 135 and within the SOI region 110. The present invention also includes a method for making the microelectronics device 100.

Abstract: In a method and system for testing a transceiver communication device operating in a test mode, a transmitter output signal generated by a transmitter is adjusted and provided as a loop back to a receiver. The adjustment includes shifting a frequency and attenuating amplitude of the transmitter output signal to substantially match a predefined frequency and a predefined amplitude of a receiver input signal received by the receiver. A pass or fail status of the device is determined by comparing transmitted and received data.

Abstract: The application discloses a data processor operable to process data, said data processor comprising: a cache having a data item storage location identified by an address; a hash value generator operable to generate a hash value from at least some of said bits of said address said hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to a plurality of storage locations within said cache; wherein in response to a request to access said data item storage location said data processor is operable to compare a hash value generated from said address with at least some of said plurality of hash values stored within said buffer. The comparison providing an indication of the storage location of the data item.

Abstract: The present invention provides a method for planarizing/polishing a surface, a method for manufacturing an integrated circuit and a chemical mechanical polishing apparatus. The method for planarizing/polishing a surface, among other elements, includes providing a chemical mechanical polishing apparatus (200, 300, 400) having a polishing platen (210, 310, 410), a carrier head (220, 320, 420) positioned over the polishing platen (210, 310, 410), and a slurry delivery source (230, 330, 430) positioned over and off center the polishing platen (210, 310, 410), and rotating the polishing platen (210, 310, 410) in a direction (Rp2, Rp3, Rp4) such that slurry exiting the slurry delivery source (230, 330, 430) and contacting the polishing platen (210, 310, 410) must rotate an angle (?2, ?3, ?4) less than about 220 degrees before contacting a polishable surface maintained by the carrier head (220, 320, 420).

Abstract: The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access