Abstract: This invention is a method of encoding intra frames when encoding a motion picture. A set of intra frame prediction modes includes a low-complexity subset. A probability table relates the prediction mode of adjacent sub-blocks to the prediction mode of the current sub-block. For each combination of adjacent sub-blocks, the probability table includes a list of prediction modes in order of expected occurrence. The probability table is adjusted so that each list for prediction modes within the low-complexity subset include initial prediction modes of the low-complexity subset. Individual sub-blocks of intra frames are predictively coded in a low-complexity encoding the using the low-complexity subset or in a high-complexity encoding using any prediction mode. This permits a low-complexity decoder responsive to only the low-complexity subset.

Abstract: A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to said master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The digital storage element operates in a functional mode or in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.

Abstract: An integrated circuit chip which has a plurality of pads and non-reflowable contact members to be connected by reflow attachment to external parts. Each of these contact members has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface on each end and a layer of reflowable material on each end. Each member is solder-attached at one end to a chip contact pad, while the other end of each member is operable for reflow attachment to external parts.

Abstract: A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.

Abstract: Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate with first and second surfaces, at least one opening, and a certain thickness. On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads; at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body attached. A semiconductor chip is positioned in the opening while leaving a gap to the substrate; the chip has an active surface including at least one bond pad, and a passive surface substantially coplanar with the second substrate surface. Substrate thickness and chip thickness may be substantially equal. Bonding elements bridge the gap to connect electrically bond pad and routing strip.

Abstract: The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also comprises melting the gate electrode to allow the dopant to diffuse throughout the gate electrode. The method further comprises re-solidifying the gate electrode to increase dopant-occupied substitutional sites within the gate electrode.

Abstract: A substrate that is not lying flat on its substrate tray can present significant process problems when a vacuum pickup attempts to pick up the substrate and fails due to the lack of a proper bond forming between the pickup and the substrate. The substrate left behind on the substrate tray could require human intervention. Intervention slows down the manufacturing process and increases costs. A method and apparatus to ensure that substrates are lying flat when presented to the vacuum pickup pad is disclosed. A plate with protrusions is raised into a substrate tray with holes. The protrusions lift the substrates up off the bottom of the substrate tray and ensure that they are laying flat when presented to the vacuum pickup pad.

Abstract: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is evaluated to determine whether a volume of last solidification for the solder is centrally located with respect to the die pad and is located at or near an interface of the solder and the die pad. If the last solidification volume is centrally located and is located at or near the interface of the solder and the die pad, and if the die pad is delaminated from the die, the structure design is modified so that less metal of the heat sink member is centrally located than before the modifying.

Abstract: Disclosed are methods and apparatus for digital control of a head-disk assembly actuator with dynamic velocity compensation. In preferred methods of the invention steps are disclosed in which, the actuator voltage in an HDA is sampled and a velocity error is determined. The voltage applied to the actuator is compensated for the velocity error. Disclosed methods of the invention also include steps for measuring the actual voltage at the actuator motor and alternatively, for calculating the actuator motor voltage using digital processing techniques. A digital voltage command is then provided for applying compensated voltage to the actuator motor. Apparatus for implementing the methods of the invention in a hard drive assembly having an actuator motor is also described.

Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.

Abstract: A timing estimation mechanism operative to generate an oversampling clock signal for a large range of reference clock frequencies without requiring use of a PLL. The oversampling timing mechanism generates appropriate timing instances, typically for the purpose of sampling a received data signal in a digital communications system, without requiring a specific external clock source but rather by utilizing a clock source having any arbitrary frequency. The mechanism of the present invention is especially suited for use in applications where a specific external clock source (e.g., integer multiple of the data rate) is not available and wherein the implications of the use of a PLL cannot be tolerated. The oversampling clock estimation mechanism generates a clock signal which may be unevenly distributed over the symbol period, but whereby on average, the correct number of samples is produced over a specific time duration.

Abstract: The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).

Abstract: A method for generating images includes shining a beam of light through a filter wheel to produce filtered light. The filter wheel includes red, green, and blue color segments and a fourth color segment that is not blue, green, red, or clear. The method also includes modulating the filtered light to form an image.

Abstract: The present application describes a system and method for determining characteristics (e.g., exact band location, orientation and height and the spot shape and size of a single wavelength and the like) of an optical signal projected on a spatial light modulator. In an embodiment, images with sharper edges (i.e. clear boundary between ‘on’ pixels and ‘off’ pixels) on the spatial light modulator are used to obtain spectral information from a referenced broadband source. The spectral information can be used to determine the desired characteristics of optical signals projected on the spatial light modulator.

Abstract: Decomposition of deblocking filters used in block-based video compression allows reduction of computational redundancies.

Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In another embodiment, the layer itself may be applied as a liquid film, using extrusion techniques.

Abstract: An isolation cell provided between a first module (which can operate in either a power-up mode or a power down mode) and a second module. According to an aspect of the present invention, the isolation cell can be located to operate drawing power from either the first module or the second module without a floating node in the power-down mode of the first module. Due to the absence of the floating nodes, unneeded power drain is reduced/avoided. In one embodiment, a switch operates to connect power to a series of pair of inverters (propagating the signal from the first module to the second module) when the first module is in power-up mode and disconnects the power in the power-down mode.

Abstract: Data processing methods and apparatus used in digital display system transpose pixel-by-pixel data into bitplane-by-bitplane data. The methods and apparatus are especially useful for dynamically transposing high-speed flowing-through pixel data in a “real-time” fashion. In a transpose process, a stream of pixel data is received by a plurality of input lines of the transpose apparatus. The received pixel data are delayed by a set of delay units and then permutated by one or more switches according to a predefined delay scheme and permutation rule. After permutation, the stream of data is delayed so as to finalize the transpose process.

Abstract: The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard ring surrounding the diode device; a diode coupled between a second end of the string of diodes and an output pad; a second NWELL guard ring surrounding the diode; and a transistor device coupled between the output pad and a substrate node. The NWELL guardrings disrupt the parasitic SCR operation by adding an additional N+ diffusion without affecting the substrate pump current delivered by the diode.