Abstract: The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access

Abstract: A provisioning mechanism installed at a customer premise equipment (CPE) device capable of Voice over Packet (VoP) communication permits provisioning of the CPE device by an auto configuration server (ACS). The provisioning mechanism includes a Capabilities object associated with the CPE device, the Capabilities object including one or more of the following: one or more fax related parameters indicative of whether the CPE device supports fax related capabilities; and a ModemPassThrough parameter indicative of whether the CPE device supports modem pass through.

Abstract: A wireless receiver is provided that includes a component and a power control logic 80. The component is operable to receive a wireless signal and process the wireless signal in at least one of a first mode and a second mode. The first mode uses less power than the second mode. The power control logic 80 is operable based on a characteristic of the wireless signal to promote processing the wireless signal by the component in the at least one of the first and second modes. A method for a wireless receiver to process the wireless signal to reduce power consumption is also provided. The method includes determining a characteristic of the wireless signal, and selecting one of a first and second modes in which to process the signal based on the characteristic of the wireless signal.

Abstract: The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.

Abstract: A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively operates in a normal mode and one or more divide modes, wherein the divide modes provide a clock frequency that is a fraction of the normal clock frequency by a divisor value that is specified in a user-accessible divider register. Lower divisor values (e.g., 2, 4, 8, etc.) are preferably used for performance tuning, while large divisor values (e.g., 1024, 2048, and 4096) are preferably used for power saving.

Abstract: A microelectromechanical device with a plastically deformable element of is exposed to illumination light so as to elongate the lifetime of the device on the customer side.

Abstract: A digital signal system (30) for determining an approximate logarithm of a value of x having a base b is described. The system comprises circuitry for storing x as a digital representation, identifying a most significant digit (MSD) of the digital representation, a table for storing a set of predetermined logarithms having the base b, circuitry for addressing the table in response to a first bit group (t) of the set of bits in respective lesser significant bit locations and for outputting a one of the predetermined logarithms corresponding to a first number (la) in the set of numbers, and circuitry for outputting the approximate logarithm of the value of x in response to the one of the predetermined logarithms and in response to a function estimation between logarithms at a first and second endpoint.

Abstract: An alignment mark to be used in conjunction with e-beam imaging to identify specific feature locations on a chip including a unique “L” shaped pattern of geometric features, which is easily detected by the recognition system of e-beam imaging equipment, and is located in close proximity to the specific circuit features under investigation at each level to be inspected. The requirements for an alignment mark design which is recognizable by state-of-the-art e-beam imaging systems are enumerated, as well as the methodology for application. The alignment marks which are included at each critical step add no cost to wafer processing, and any design cost is easily overcome by reduction in process development time by using defect learning.

Abstract: This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.

Abstract: A distributed method and apparatus for assigning a unique identifier number to devices connected in a sequential fashion and determining a total device count is presented. Additionally, a method and apparatus for enabling the support of a variable number and type of time slots within a time division multiplexed serial protocol is presented.

Abstract: An ADSL transceiver hybrid circuit uses one or more isolated couplers (optical couplers, capacitors, or the like) configured to minimize the transmit signal component in the receive signal path by providing an isolated transmit signal feedback, thereby providing echo cancellation, isolating the telephone loop from the analog front end, and eliminating the need for a complex high-pass filter. The ADSL transceiver provides isolation and echo cancellation by: (a) generating a signal within the analog loop (e.g., telephone loop, or “local loop”) corresponding to a differential transmit signal; (b) receiving a composite signal from the analog loop corresponding to the sum of the transmit signal generated on the analog loop and the receive signal; (c) producing an isolated transmit signal (e.g.

Abstract: The invention provides tester load board shields (10, 40) for attachment to tester load boards. The shields (10, 40) of the invention protect from physical damage and electromagnetic interference. A preferred embodiment of a tester load board shield (10) of the invention is disclosed in which a disc (12) and outer rim (14) of conductive metal such as aluminum or aluminum alloy are configured to accept a tester load board. The tester load board shield (10) has holes (18) to align with a selected tester load board for attachment of the shield (10) thereto. Stanchions (22) are provided to facilitate attachment of the Loadboard with shield (10) to automatic test equipment known in the arts while a tester load board, also familiar in the arts, is fastened to the shield (10). Another embodiment of a tester load board shield (40) is disclosed in the shape of annulus (42) configured to contain a tester load board within an outer rim (44), planar surface (46), and inner rim (50).

Abstract: A technique to enhance performance and reduce silicon area for a TCAM system which includes a plurality of CAM blocks that are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of TCAM cells and associated read/write bit lines connecting the group of CAM cells to search bit lines. Each TCAM cell in the TCAM architecture includes a pair of memory elements that is connected to a pair of associated compare circuits such that the interconnections between the memory elements and the compare circuits are substantially vertical in active MOS layers and substantially horizontal in the metal layers to facilitate sharing of adjacent cells thereby providing reduced silicon area and a short aspect ratio.

Abstract: This invention comprises a two part audio system in which all of the processing power is allocated to a small, lightweight satellite part that is the face unit. Mass storage, amplification, and wired power for recharging the face unit is provided by the other part, the base. The base runs either from a 120 volts AC source or 12 volts DC. The face unit contains a small amount of flash memory making it capable of carrying music normally stored on two or more compact discs (CDS).

Abstract: According to one embodiment of the invention, a system for packaging integrated circuits includes a mold tool for packaging integrated circuits. The mold tool includes a first mold plate that includes a first non-planar surface and a second mold plate that includes a second non-planar surface. The first and second non-planar surfaces form upper and lower surfaces of a mold cavity when the first and second mold plates are engaged. The mold tool also includes a distribution system coupled to the mold cavity. The distribution system transfers a mold compound into the mold cavity to substantially encapsulate an integrated circuit. The distribution system includes a gate runner coupled to the mold cavity. The gate runner funnels the mold compound into the mold cavity. The distribution system also includes a bridge insert that decreases wear on the gate runner as the mold compound is transferred through the gate runner.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: A printer controller in which the image data received in indexed format is stored only in indexed format. The image data is converted to long format when required for rendering operations by using an appropriate lookup table. By storing the image data only in indexed format until the time of rendering, the memory requirements within a system may be minimized. According to another aspect of the present invention, floating point operations (providing higher precision) may be used in a interpreter block and fixed point operations (providing more speed) may be used in a rendering block, while avoiding/reducing image artifacts in upscaled images. A check is performed to determine whether a pixel in the upscaled image maps back to fall within the boundary of the source image, and corrective action is taken if the pixel does not fall within the boundary.

Abstract: According to one embodiment, a method of analyzing semiconductor test data includes receiving a plurality of raw data entries from a testing system. Each raw data entry is associated with a test structure of a semiconductor device, and each raw data entry is uniquely identified by a name including a plurality of parseable fields. The plurality of data entries is parsed using a selected one of the plurality of parseable fields to identify a grouping of raw data entries. At least one reportable parameter indicative of the functionality of the test structures associated with the grouping of raw data entries is calculated, and the at least one reportable parameter is provided to a user.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while mitigating masking operations employed. A CAPOLY layer is formed over an NMOS region of a semiconductor device (102). A recess etch is performed on active regions of devices within a PMOS region of the semiconductor device (104) and the CAPOLY layer prevents etching of devices within an NMOS region of the semiconductor device. Subsequently, an epitaxial formation process (106) is performed that forms or deposits epitaxial regions and introduces a first type of strain across the channel regions in the PMOS region. Then, the semiconductor device is annealed (108) to cause the CAPOLY layer to introduce a second type of strain across the channel regions in the NMOS region. After annealing, the CAPOLY layer is removed (110).

Abstract: A method to improve an extinction ratio of an optical device, the method includes positioning at least a majority of a plurality of micro-mirrors in an off-state position. A mirror assembly includes the plurality of micro-mirrors. The method also includes selectively positioning at least one of the plurality of micro-mirrors in an on-state position. In one particular embodiment, the at least one of the plurality of micro-mirrors positioned in the on-state position operates to improve an extinction ratio of an optical device.