Patents Assigned to Texas Instruments
  • IC output signal path with switch, bus holder, and buffer
    Publication number: 20070011546
    Abstract: An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit (121B), and an output buffer (19).
    Type: Application
    Filed: July 27, 2006
    Publication date: January 11, 2007
    Applicant: Texas Instruments Incorporated
    Inventor: Lee Whetsel
  • Method and System for Applying an Adhesive Substance on an Electronic Device
    Publication number: 20070006805
    Abstract: According to one embodiment of the invention, a system for applying an adhesive substance to an electronic device having a region designated to be coupled to another device is provided. The region has a first shape defined by a first boundary. The system includes a tube having an open end. The system also includes a nozzle having an opening coupled to the open end of the tube. The opening has a second shape that is approximately the same as the first shape.
    Type: Application
    Filed: September 18, 2006
    Publication date: January 11, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Mark Cruz, Jinky Cruz, Jerry Cayabyab
  • Method to obtain fully silicided poly gate
    Publication number: 20070010062
    Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a spacer material 160 over gate electrodes 150 that are, in turn, located over a microelectronics substrate 110. The gate electrodes 150 have a doped region 170a located between them. A portion of the spacer material 160 is removed with a chemical/mechanical process using a slurry that is selective to a portion of the spacer material 160. The method further comprises etching a remaining portion of the spacer material 163, 165, 168 to form spacer sidewalls 163, 165, 168 on the gate electrodes 150. The etching exposes a surface of the gate electrodes 150 and leaves a portion of the spacer material 168 over the doped region 170a. Metal is then incorporated into the gate electrodes 150 to form silicided gate electrodes 150.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 11, 2007
    Applicant: Texas Instruments, Incorporated
    Inventors: Freidoon Mehard, Shafoeng Yu, Joe Tran
  • Synchronizing stack storage
    Patent number: 7162586
    Abstract: A system comprises a main stack, a local data stack and plurality of flags. The main stack comprises a plurality of entries and is located outside a processor's core. The local data stack is coupled to the main stack and is located internal to the processor's core. The local data stack has a plurality of entries that correspond to entries in the main stack. Each flag is associated with a corresponding entry in the local data stack and indicates whether the data in the corresponding local data stack entry is valid. The system performs two instructions. One instruction synchronizes the main stack to the local data stack and invalidates the local data stack, while the other instruction synchronizes the main stack without invalidating the local data stack.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Serge Lasserre
  • Method for enhancing rendering of picture elements
    Patent number: 7161690
    Abstract: For a given lookup table, maximum and minimum values of index values are determined. The lookup table is expanded in both directions by replicating the lowest and highest values to take care of these maximum and minimum values. This reduces the rendering clock count for each pixel.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Danke Mahesh Bhaskar
  • Wireless packet communications with extended addressing capability
    Patent number: 7161941
    Abstract: In packet communications, one existing address code in a predetermined address field (AM_ADDR) of a packet can be used to indicate that bits in another field (TYPE) of the packet represent additional address information. Additional address information can also be provided for by extending the length of the predetermined address field.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy M. Schmidl, Mohammed Nafie, Anand G. Dabak
  • Programmable extended compression mask for dynamic trace
    Patent number: 7162552
    Abstract: This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace address that do not match the comparison address or are less significant than any section of the current trace address that does not match the comparison address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The comparison address is specified by a central processing unit via a memory mapped register write operation.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Lewis Nardini, Manisha Agarwala, John M. Johnsen
  • Position demodulation through polarization of the transmitted beam in an optical wireless link
    Patent number: 7162159
    Abstract: A method of eliminating the non-linearities associated with the remote feedback sensor, such as a quad position detector, used in a micro-electro-mechanical (MEM) mirror assembly. The incoming beam transmitted from a remote optical wireless link is first polarized, and then a single detector is employed to detect the polarization for the receiver. The single detector eliminates the non-linearity associated with a quad position detector, since the space between the quad detectors is eliminated.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Eric G. Oettinger, Robert E. Jansen
  • Efficient encoder for low-density-parity-check codes
    Patent number: 7162684
    Abstract: Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which a left-hand portion of the parity check matrix is arranged as an identity macro matrix, each entry of the macro matrix corresponding to a permutation matrix having zero or more circularly shifted diagonals. The encoder circuitry includes a cyclic multiply unit, which includes a circular shift unit for shifting a portion of the information word according to shift values stored in a shift value memory for the matrix entry, and a bitwise exclusive-OR function for combining the shifted entry with accumulated previous values for that matrix entry. Circuitry for solving parity bits for row rank deficient portions of the parity check matrix is also included in the encoder circuitry.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Dale E. Hocevar
  • Method for enhancing the visibility of effective address computation in pipelined architectures
    Patent number: 7162618
    Abstract: The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in the pipeline is calculated. The current effective address delay is used to determine if a valid effective address is available for each instruction. If a valid effective address for an instruction is not available, it is computed if possible.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Edward P. Kuzemchak, Christine M. Cipriani, Christophe Favergeon-Borgialli, Mary P. Luley
  • Method of manufacture for a trench isolation structure having an implanted buffer layer
    Patent number: 7160782
    Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Rick L. Wise, Mark S. Rodder
  • Digital system and method for displaying images using shifted bit-weights for neutral density filtering applications
    Patent number: 7161608
    Abstract: Disclosed herein are visual display systems and methods capable of having shifted bit-weights in neutral density filtering (NDF) applications. In one embodiment, a method (200) of displaying an image comprises transmitting light through an optical filter (17) comprising at least one high transmissivity portion configured to output light at an initial intensity, and at least one low transmissivity portion configured to output light at a lower intensity than the initial intensity, where the initial intensity and lower intensity output light illuminates a spatial light modulator (14). The method also includes providing a plurality of data bits (non-ND) from a predetermined number of data bits (B0–B7), where each of the plurality comprises a pulse-width longer than a load-time for operating the spatial light modulator (14).
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory S. Pettitt, Harold E. Bellis, II, Jason R. Thompson, James F. Headley, Dana F. Segler, Jr.
  • Dynamic data trace output scheme
    Patent number: 7162411
    Abstract: Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Manisha Agarwala, Maria B. H. Gill, John M. Johnsen
  • Method of inspecting a mask
    Patent number: 7160650
    Abstract: The invention relates to a method of inspecting a mask comprising the steps: patterning a semiconductor material with a reference mask, patterning the semiconductor material with the mask as the inspection item, inspecting both patterns on the semiconductor material by means of an apparatus suitable for inspecting the semiconductor material, and comparing the pattern generated by the inspection item mask to the pattern generated by the reference mask to detect deviations in the inspection item mask from the reference mask. The invention is particularly suitable for reticule inspection. When a semiconductor wafer is multiply patterned by the reference mask and the inspection item mask alternatingly side-by-side, deviations in the reticules are evident as recurrent discrepancies between the patterns on the wafer.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Christoph Hechtl, Jens Lohse, Peter Schäffler
  • Multi-stage analog to digital converter architecture
    Patent number: 7161521
    Abstract: According to an aspect of the present invention, different reference voltage levels are used for different stages of a multi-stage analog to digital converter (ADC). In one embodiment, the amplification and unity gain bandwidth (UGB) requirements in the first stage is reduced as a result.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gautam Salil Nandi, Visvesvaraya A. Pentakota, Nitin Agarwal, Sandeep Kesrimal Oswal
  • Transmit and receive window synchronization
    Patent number: 7161978
    Abstract: A system for synchronizing sender sliding windows and receiver sliding windows employed in wireless packet communication is provided. The sender sliding window buffers outgoing packets to be sent to a receiver that employs a receiver sliding window to buffer incoming packets. A sender window manager manages the sender sliding window through positive acknowledgement, negative acknowledgement and/or timeout processing to facilitate synchronizing the sender sliding window with the receiver sliding window without employing synchronization messages or master/slave control. Similarly, a receiver window manager manages the receiver sliding window through sequence number analysis to facilitate synchronizing the receiver sliding window with the sender sliding window without employing synchronization messages or master/slave control.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaolin Lu, Ping Tao, Michael O. Polley
  • Integrated circuit dynamic parameter management in response to dynamic energy evaluation
    Patent number: 7162652
    Abstract: A power management system (12) in an electronic device (10). The system comprises circuitry (14x), responsive to at least one system parameter, for providing data processing functionality, where the circuitry for providing data processing functionality comprises a data path (CPx). The system alternatively or cumulatively also comprises circuitry (22x) for indicating a potential capability of operational speed of the data path and/or circuitry (24x) for indicating an amount of current leakage of the circuitry for providing data processing functionality. The system also comprises circuitry (26) for adjusting the at least one system parameter in response to either or both of the circuitry for indicating a potential capability and the circuitry for indicating an amount of current leakage.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Sami Issa, Uming Ko, Baher Haroun, David Scott
  • Arrangement in Semiconductor Packages for Inhibiting Adhesion of Lid to Substrate While Providing Compression Support
    Publication number: 20070004083
    Abstract: In a semiconductor flip-chip package having a semiconductor die as part of a substrate assembly, a lid (or lid assembly) and substrate are supported to prevent tilting and teetering of the lid. The lid and substrate do not adhere, so as to reduce cracking of solder joints due to thermal cycling induced by repeated system power on-off. An adhesion prohibitor may be applied so that a support does not adhere to both lid and substrate; the support may be prevented from adhering to both lid and substrate by a separate curing step. The arrangements and fabrication methods may be applied to many package types, including ball grid array (BGA) and land grid array (LGA) packages.
    Type: Application
    Filed: September 6, 2006
    Publication date: January 4, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Tz-Cheng Chiu, Rajiv Dunne
  • Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality
    Publication number: 20070001733
    Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Charles Branch, Steven Bartling, Dharin Shah
  • METHOD AND SYSTEM OF INDEXING INTO TRACE DATA BASED ON ENTRIES IN A LOG BUFFER
    Publication number: 20070006174
    Abstract: A method and system of indexing into trace data based on entries in a log buffer. At least some of the illustrative embodiments are methods comprising executing a traced program on a target device. The traced program writes entries to a log buffer within the target device, and the traced program also contemporaneously writes an index value for each entry to a register. The index value written to the register becomes part of trace data regarding the traced program and correlates each entry to a respective portion of the trace data. Using the information one may either or both: display on a display device a portion of the trace data (the portion selected based on selecting an entry from the log buffer); or display on the display a portion of the log buffer (the portion selected based on selecting an entry from the trace data).
    Type: Application
    Filed: May 15, 2006
    Publication date: January 4, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank, Manisha Agarwala