Patents Assigned to Texas Instruments
  • Patent number: 7088274
    Abstract: An improved circuit is provided that buffers the output of a DAC while improving the bandwidth and linearity of the circuit. A DAC comprises an output signal of a switched DAC circuit coupled to an inverting node of an output buffer configured as a difference amplifier, while a non-inverting node of the difference amplifier is coupled to a fixed reference potential. As a result, the difference amplifier buffers the output of the switched DAC circuit while permitting the use of N-type input stages in the amplifier, which can enhance the bandwidth capability of the circuit.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Mark Allan Shill
  • Patent number: 7088785
    Abstract: Space time transmit diversity (9, 14, 17, 19) is applied at the block level to an original block of bits (12) in order to reduce the effects of fading in wireless communication systems that use nonlinear modulation schemes (13, 33). At the receiving end, fading parameters (?1, ?2) are estimated (?E1, ?E2) and the properties of complex conjugates are utilized (28, 29, 201, 202) to produce a result (r1, r2) that is representative of the original block of bits.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Mohammed Nafie, Anand G. Dabak
  • Patent number: 7088171
    Abstract: An improved charge pump circuit that is capable of producing a constant output current. The charge pump circuit includes a controllable current source, at least one switching element coupled between the controllable current source and an output node, and a load capacitor coupled between the output node and ground potential. The switching element switches in response to an input signal to allow current pulses to flow from the controllable current source through the output node. The load capacitor operates as an integrator to convert the output current pulses into a voltage level. The controllable current source provides increased current levels as the output voltage level of the charge pump increases, thereby enhancing the overall efficiency of the charge pump circuit.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Robert Alan Neidorff
  • Patent number: 7088791
    Abstract: Systems and methods are provided for performing signal processing on communication data utilizing scale reduced Fast Fourier Transform computations. The present invention provides scaling in a Fast Fourier Transform computation at stages where it is determined that bit growth is present and omits scaling at stages where it is determined that bit growth is absent. The determination is based on the characteristics of the input signal. The determination can be made off-line by modeling and/or simulation or in real-time by analyzing the input signal to determine stages at which bit growth is present and/or absent and setting the stage scaling accordingly.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: David Patrick Magee
  • Patent number: 7087493
    Abstract: A method of forming a memory circuit comprising six transistor memory cells. The memory cells comprise first and second inverters. The inverters comprise respective first and second drive transistors and first and second pull-up transistors. The method also forms a plurality of conducting plugs. A first conducting plug is coupled to the first inverter and a second conducting plug is coupled to the first pull-up transistor and to the gates of the second drive transistor and the second pull-up transistor. A third conducting plug is coupled to the second inverter and a fourth conducting plug coupled to the second pull-up transistor and to the gates of the first drive transistor and the first pull-up transistor. The method also forms conducting elements. A first conducting element contacts the first conducting plug and the second conducting plug and a second conducting element contacts the third conducting plug and the fourth conducting plug.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Sudhir K. Madan
  • Patent number: 7087479
    Abstract: Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (130). Contacts are formed to the conductive layer (80) by etching openings in the carbon containing dielectric layer (140) and the optional dielectric layer (130).
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Leland S. Swanson, Gregory E. Howard
  • Patent number: 7088602
    Abstract: A DC-DC converter circuit includes a transformer with a resonate filter or snubber connected at a primary side and a switch for controlling operation of the converter. A secondary side of the transformer includes self-driven synchronous rectifiers and an output filter. Transistors are provided at the gates leads of the rectifiers and themselves are provided with a fixed voltage at their gates so as to clamp the peak voltages across to the rectifiers.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Robert A. Priegnitz, Charles A. Devries, Jr.
  • Patent number: 7089437
    Abstract: In order to measure the power consumed by a bus in a digital signal processor, each bus conductor has a lead electrically coupled thereto. The lead is coupled to apparatus that provides a signal each time the logic state of the bus is changed. The total number of logic signal changes for a given period of time is determined. Because power is consumed by the bus only during logic state transitions, the total number of logic state transitions can be multiplied by the power consumed by the bus during each transition to provide the total power consumed during a predetermined period of time. The power consumed by the bus during each logic state transition can be determined by simulation or other techniques. The power consumed by the operation of the bus can be further divided into power consumed by the internal (on-chip) bus and the external (off-chip) bus.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 7088182
    Abstract: A class-AB output stage circuit is configured with controllable reference voltages for providing stable quiescent current. An exemplary output stage circuit comprises one or more control circuits, such as feedback loops, configured to control and/or adjust the reference voltages within the class-AB circuit based on the output voltage and/or supply rail voltage levels. In addition, an exemplary output stage circuit can also comprise one or more clamp circuits configured to facilitate operation of the output stage circuit when the output supply is proximate to or exceeds a positive or a negative supply rail.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Vadim V. Ivanov
  • Patent number: 7089183
    Abstract: A new iterative hierarchical linear regression method for generating a set of linear transforms to adapt HMM speech models to a new environment for improved speech recognition is disclosed. The method determines a new set of linear transforms at an iterative step by Estimate-Maximize (EM) estimation, and then combines the new set of linear transforms with the prior set of linear transforms to form a new merged set of linear transforms. An iterative step may include realignment of adaptation speech data to the adapted HMM models to further improve speech recognition performance.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Yifan Gong
  • Patent number: 7088607
    Abstract: The objective of this invention is to provide a static memory cell and an SRAM device that can improve the write margin while preventing degradation of the static noise margin. By turning on/off transistor Qp13, it is possible to control the drop in voltage due to the threshold voltage of transistor Qn15. For example, in read mode, when it is necessary to hold the stored data while setting word line WL to the high level, transistor Qp13 is turned off; the drivability of transistor pair Qn11, Qn12 is decreased, thereby increasing the static margin. In the case of rewriting the stored data, transistor Qp13 is turned on; the drivability of transistor pair Qn11, Qn12 is increased, thereby increasing the write margin. As a result, it is possible to improve the performance of both the static noise margin and the write margin.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Takahiro Matsuzawa, Yoritaka Saitoh, Masayuki Hira
  • Publication number: 20060171488
    Abstract: A communications receiver is provided that includes a first and second compensators 64 and 68, a pilot tracker 60, and a demodulator 66. The first compensator 64 is operable to adjust an input signal based on both a coarse frequency offset and a fine frequency offset to produce an adjusted input signal. The pilot tracker 60 determines an estimated residual frequency offset based on at least a portion of the adjusted input signal. The demodulator 66 determines at least a first symbol sequence and a second symbol sequence based on the adjusted input signal. The second compensator 68 is operable to adjust the first symbol sequence and the second symbol sequence based on the estimate residual frequency offset.
    Type: Application
    Filed: January 28, 2005
    Publication date: August 3, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: John Rosenlof, Kirupairaj Asirvatham, Srikanth Gummadi
  • Publication number: 20060170661
    Abstract: An electronic device (18). The device comprises an analog (16) interface for receiving an analog waveform. The device also comprises an image screen (20) and circuitry (42) for at times displaying an image on the image screen in response to at least a portion of the analog waveform. The device also comprises a memory (48) for storing firmware code and circuitry (44, 46) for at times writing firmware code in the memory in response to at least a portion of the analog waveform.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 3, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Steven Clynes, Kevin Chalmers
  • Publication number: 20060172545
    Abstract: The present invention provides, in one embodiment, a method for reducing defects associated with a plasma deposition or etching process. In this particular embodiment, the method includes creating a plasma in a deposition or etching chamber (140) and purging undesirable species from the deposition or etching chamber (150) in the presence of the plasma.
    Type: Application
    Filed: February 2, 2005
    Publication date: August 3, 2006
    Applicant: Texas Instruments, Inc.
    Inventors: Kenneth Hewes, Mark Odom, Michael Satterfield, Sirisha Kuchimanchi, Sean Collins, Zaid Nahas
  • Publication number: 20060170825
    Abstract: A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also comprises circuitry for processing the S analog input signals, and that circuitry comprises an integer number N of analog-to-digital converters (38x) for producing a set of the integer number S of digital signals. Each digital signal in the set of S of digital signals corresponds to a respective different one of the S analog input signal, and N is less than S. The decoder also comprises output circuitry (40x, 42x), coupled to the circuitry for processing, for providing each digital signal in the set of S of digital signals to a different respective output conductor.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 3, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Towfique Haider, Jason Meiners
  • Publication number: 20060171221
    Abstract: The present invention provides a method for analyzing critical defects in analog integrated circuits. The method for analyzing critical defects, among other possible steps, may include fault testing a power field effect transistor (120) portion of an analog integrated circuit (115) to obtain electrical failure data. The method may further include performing an in-line optical inspection of the analog integrated circuit (115) to obtain physical defect data, and correlating the electrical failure data and physical defect data to analyze critical defects.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 3, 2006
    Applicant: Texas Instruments, Inc.
    Inventors: Martin Mollat, Milind Khandekar, Tony Phan, Kyle Flessner
  • Publication number: 20060172443
    Abstract: The present invention provides a method detecting metal silicide defects in a microelectronic device. The method comprises positioning (110) a portion of a semiconductor substrate in a field of view of an inspection tool. The method also comprises producing (120) a voltage contrast image of the portion, wherein the image is obtained using a collection field that is stronger than an incident field. The method further comprises using (130) the voltage contrast image to determine a metal silicide defect in a microelectronic device. Other aspects of the present invention include an inspection system (200) for detecting metal silicide defects and a method of manufacturing an integrated circuit (300).
    Type: Application
    Filed: February 2, 2005
    Publication date: August 3, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Deepak Ramappa
  • Publication number: 20060172556
    Abstract: The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure (230) over a substrate (210), and forming a strain inducing film (330, 520, 530 or 810) over the substrate (210) and proximate the gate structure (230), the strain inducing film (330, 520, 530 or 810) comprising a bis t-butylaminosilane (BTBAS) silicon nitride layer formed using ratio of bis t-butylaminosilane (BTBAS) to ammonia (NH3) of 1:1 or greater.
    Type: Application
    Filed: February 1, 2006
    Publication date: August 3, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Wayne Bather, Narendra Mehta, Troy Yocum
  • Publication number: 20060171445
    Abstract: In at least some embodiments, a method for mitigating interference between an Ultra Wideband (UWB) device and a non-UWB device is provided. The method includes, dynamically determining if a frequency channel associated with the non-UWB device is being used. If the frequency channel is being used, the method adjusts a UWB frequency band used for UWB signal transmission.
    Type: Application
    Filed: January 27, 2006
    Publication date: August 3, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Anuj Batra, Jaiganesh Balakrishnan, Srinivas Lingam
  • Patent number: 7084611
    Abstract: The invention relates to a DC/DC converter including an input to which an input voltage Vin is applied, a inductance L whose one terminal is connected to the input, a first controllable switch N1 via which the other terminal of the inductance is connectable to a reference potential Vss, a second controllable switch P1 via which the other terminal of the inductance is connectable to the output of the converter, and a regulator circuit 1 configured so that it is able to control the two switches in regulating the output voltage of the DC/DC converter to a predetermined wanted value. The second controllable switch is a PMOS-FET.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: August 1, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Joerg Kirchner, Thomas Keller, Christian Schimpfle