Abstract: The present invention provides a pre-channel estimate phase corrector for use with a multiple-input, multiple-output (MIMO) receiver employing M receive antennas, where M is at least two. In one embodiment, the pre-channel estimate phase corrector includes a training sequence coordinator configured to receive a pattern of training sequences from the M receive antennas during preamble symbol time periods. Additionally, the pre-channel estimate phase corrector also includes a phase calculator coupled to the training sequence coordinator and configured to calculate phase corrections prior to establishing individual channel estimates based on the pattern of training sequences.

Abstract: Providing TDM channels to locations connected by networks implemented on broadcast medium. An (sender) interface equipment receives data bits of frames from a TDM node, forms data packets from the data bits, and sends the data packets on a broadcast network to a receiver interface equipment. The receiver interface equipment receives the data packets, generates frames for transmission to another TDM end node, and transmits the frames to the another TDM end node. The clock signal of the broadcast network may be used as a reference signal to provide a clock signal having an equal frequency to the clock signal used by the sender interface equipment to receive data on TDM channels.

Abstract: A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises sequencing through a sequence of the states, and detecting a predetermined sequence of the states. The predetermined sequence of the states represents a no-operation for at least one of the modes and also represents a mode change command.

Abstract: A CMOS operational amplifier with a Class AB output stage has an output terminal and an input stage driving the output stage. The Class AB output stage includes a pair of p-channel and n-channel output transistors series-connected between the VDD and VSS supply terminals of a power supply. Each of the output transistors has associated biasing circuitry with a pair of positive and negative driving inputs and a biasing input. The input stage has driving outputs connected to corresponding ones of the driving inputs of the output stage. Each driving output is derived from the drain of a MOS transistor connected in series with a diode connected MOS transistor between the VDD and VSS supply terminals. By avoiding the conventional stacked MOSFETs that would set the minimum supply voltage to more than two threshold voltages, the op-amp can be operated over the full range of supply voltage.

Abstract: A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post.

Abstract: Image content may be generated in high resolution by performing raster operations, and half-toning is then performed on the image content. Due to such a sequence, a substantially consistent image may be generated on different printers irrespective of the degree of half-toning. Another aspect of the present invention enables the computation requirements to be reduced by storing in a temporary buffer the image data (paint, destination, source) used multiple times.

Abstract: A gate structure (30) is formed over a semiconductor (10). Sidewall structures (200) of a first width W1 are formed adjacent to the gate structure (30) and source and drain regions (90) are formed in the semiconductor (10). An etch process is performed to reduce the width of the sidewall structure to W2 and silicide regions (110) are then formed adjacent to the sidewall structures (205).

Abstract: A bipolar rail-to-rail class-AB output stage that provides improved AC performance in low voltage applications. The bipolar output stage includes an input buffer stage, first and second complementary common emitter stages, and first and second control circuits biased and configured to assure class-AB operation of the first and second common emitter stages, respectively. The input of the bipolar output stage is applied to the input buffer stage, and the output of the bipolar output stage is provided by the second common emitter stage. The combination of the first common emitter stage and the first AB-control circuit operates as a current booster stage for the second common emitter stage, thereby obviating the need for a large power supply.

Abstract: A variety of bi-directional data transmission systems that facilitate communications between a plurality of remote units (15) and a central unit (10) using a frame based discrete multi-carrier transmission scheme are disclosed. In each of the systems, frames transmitted from the plurality of remote units (15) are synchronized at the central unit (10). A variety of novel modem arrangements and methods for coordinating communications between a plurality of remote units (15) and a central unit (10) to facilitate multi-point-to-point transmission are disclosed. The invention has application in a wide variety of data transmission schemes including Asymmetric Digital Subscriber Line systems that include the transmission of signals over twisted pair, fiber and/or hybrid telephone lines, cable systems that includes the transmission of signals over a coaxial cable, and digital cellular television systems that include the transmission of radio signals.

Abstract: A method and mechanism for cooling a display device, having an extremely bright light focused on its surface and is mounted inside a closed chassis, by conducting heat from the device directly to the chassis walls, where the heat is then transferred to the lower temperature air of the ambient surroundings. The mechanism uses an adjustable mechanical linkage to close the gap and make a good thermal contact between the projection device package or heat sink stud and the chassis wall. This approach reduces the requirements for large heat sinks and noisy cooling fans found in many conventional projection systems.

Abstract: A DC—DC CMOS converter including when the supply voltage is low, the current limit is automatically reduced to the maximum possible value that maintains the comparator operative, rather than simply switching off the converter.

Abstract: A dynamic current generator 30 is disclosed in which a common-mode input range is provided which is asymmetric toward the bottom rail VEE. An embodiment of the invention is also disclosed used in an asymmetrical dynamically biased amplifier system 34.

Abstract: Methods and systems are provided for dynamically managing power consumption in a digital system. These methods and systems broadly provide for permitting clients executing on a digital system to register for notification of power event and to request that power events occur. Registered clients are notified when a power event is requested and the requested power event is caused to occur. Power events are selected from a group comprising setpoint change, enter deep sleep mode, enter snooze mode, and change to power supply status. There may also be user-defined custom power events. If the requested power event is a setpoint change, a check is made to verify that each of the registered clients can operate at the requested setpoint. The digital system may be comprised of processor with a single processing core with a single clock or a processor with multiple processing cores and multiple clocks.

Abstract: A GTL output structure having an active charging and discharging stage that actively restores internal nodes for slew rate control without the need to wait for a slow rise and fall RC time constant is disclosed herein. The novel GTL output structure includes an input stage connected to an RC network for providing slew rate control. The output stage connects between the RC network and a feedback network. The feedback network in includes an active charging stage for providing a charging current to the gate of the at least one transistor for a period of time to the value of a power supply rail and wherein the feedback network includes an active discharging stage for providing a discharge current from the gate of the at least one transistor to ground.

Abstract: Disclosed is a method of making a mold lock for bonding leadframe-to-plastic in an IC package. Steps include providing niches from opposing sides of the leadframe. The opposing niches are arranged such that an aperture and a mechanical key are formed within the leadframe material by the partial intersection of the niches. The key is encapsulated with mold compound to form a lock. An IC package mold lock in a leadframe is also disclosed, the lock having an aperture, a key, and mold compound encapsulating the key. Additionally, an IC package employing the leadframe-to-plastic lock is disclosed.

Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

Abstract: A memory circuit and method for reducing gate oxide stress is disclosed. A first data word is stored at a first address in a nonvolatile memory circuit 604. The first address 820 and the first data word 842 are stored in a volatile memory circuit 602. A first external address 608 is applied to the volatile memory circuit. The first external address is compared to the first address. The first data word is produced from the volatile memory circuit on a data bus 610 when the first external address matches the first address. The first data word is produced from the nonvolatile memory circuit on the data bus when the first external address does not match the first address.

Abstract: A method of image/video compression with intra-coding blocks analyzed for sum of absolute magnitudes of AC coefficients of DCT of block to determine whether to approximate the block with 0 AC coefficients, and with inter-coding blocks analyzed for sum of absolute differences of block and predicted block to determine whether to approximate the block with a 0 block.

Abstract: A bit-error-rate (BER) test is a crucial test for wireless devices to pass, since a device with a high BER does not perform at its best. BER tests are both costly and difficult to perform due to a delay incurred by the device under test (DUT) 215 and the testing hardware that is variable in nature. Because the delay is variable, a hardware BER test that can compensate for the delay is difficult to build and a software BER test that can easily compensate for the delay is very slow. The present invention provides a method and apparatus that can compensate for the variable delay. By doing so, a hardware BER test, which is considerably faster than a software BER test, is easily implemented.

Abstract: An ADSL receiver HPF architecture 300 that reduces the number of Op Amps below that required for known ADSL receiver HPFs. The ADSL receiver HPF 300 is implemented as an active RC filter to provide a single fifth-order Elliptic filter instead of the more conventional pair of third-order Elliptic filters. Since the HPF Elliptic filter stage having the lowest Q factor is reduced as the order of an Elliptic filter transfer function is increased, a single fifth-order Elliptic filter suitable for use as an ADSL receiver HPF can be implemented using only one Op Amp in the second 2nd-order HPF stage 308. A notch (imaginary zero) is provided by summing of output signals associated with active RC structure state variables. This structure minimizes the number of capacitors while preserving the capability to provide a high Q factor for the first 2nd-order HPF stage 304.